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Properly pseudo-ize MOVCCr and MOVCCs.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127434 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-03-10 23:56:09 +00:00
parent c9f2f61d34
commit d4a16ad85d
4 changed files with 41 additions and 32 deletions
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27
lib/Target/ARM/ARMExpandPseudoInsts.cpp
View File

@ -708,6 +708,33 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
switch (Opcode) {
default:
return false;
case ARM::MOVCCr: {
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVr),
MI.getOperand(1).getReg())
.addReg(MI.getOperand(2).getReg(),
getKillRegState(MI.getOperand(2).isKill()))
.addImm(MI.getOperand(3).getImm()) // 'pred'
.addReg(MI.getOperand(4).getReg())
.addReg(0); // 's' bit
MI.eraseFromParent();
return true;
}
case ARM::MOVCCs: {
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs),
(MI.getOperand(1).getReg()))
.addReg(MI.getOperand(2).getReg(),
getKillRegState(MI.getOperand(2).isKill()))
.addReg(MI.getOperand(3).getReg(),
getKillRegState(MI.getOperand(3).isKill()))
.addImm(MI.getOperand(4).getImm())
.addImm(MI.getOperand(5).getImm()) // 'pred'
.addReg(MI.getOperand(6).getReg())
.addReg(0); // 's' bit
MI.eraseFromParent();
return true;
}
case ARM::Int_eh_sjlj_dispatchsetup: {
MachineFunction &MF = *MI.getParent()->getParent();
const ARMBaseInstrInfo *AII =

35
lib/Target/ARM/ARMInstrInfo.td
View File

@ -3152,32 +3152,15 @@ def BCCZi64 : PseudoInst<(outs),
// the normal MOV instructions. That would fix the dependency on
// special casing them in tblgen.
let neverHasSideEffects = 1 in {
def MOVCCr : AI1<0b1101, (outs GPR:$Rd), (ins GPR:$false, GPR:$Rm), DPFrm,
IIC_iCMOVr, "mov", "\t$Rd, $Rm",
[/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $Rd">, UnaryDP {
bits<4> Rd;
bits<4> Rm;
let Inst{25} = 0;
let Inst{20} = 0;
let Inst{15-12} = Rd;
let Inst{11-4} = 0b00000000;
let Inst{3-0} = Rm;
}
def MOVCCs : AI1<0b1101, (outs GPR:$Rd),
(ins GPR:$false, so_reg:$shift), DPSoRegFrm, IIC_iCMOVsr,
"mov", "\t$Rd, $shift",
[/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $Rd">, UnaryDP {
bits<4> Rd;
bits<12> shift;
let Inst{25} = 0;
let Inst{20} = 0;
let Inst{19-16} = 0;
let Inst{15-12} = Rd;
let Inst{11-0} = shift;
}
def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
Size4Bytes, IIC_iCMOVr,
[/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $Rd">;
def MOVCCs : ARMPseudoInst<(outs GPR:$Rd),
(ins GPR:$false, so_reg:$shift, pred:$p),
Size4Bytes, IIC_iCMOVsr,
[/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $Rd">;
let isMoveImm = 1 in
def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, i32imm_hilo16:$imm),

4
test/CodeGen/ARM/long_shift.ll
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@ -26,7 +26,7 @@ define i32 @f2(i64 %x, i64 %y) {
; CHECK-NEXT: rsb r3, r2, #32
; CHECK-NEXT: subs r2, r2, #32
; CHECK-NEXT: orr r0, r0, r1, lsl r3
; CHECK-NEXT: movge r0, r1, asr r2
; CHECK-NEXT: asrge r0, r1, r2
%a = ashr i64 %x, %y
%b = trunc i64 %a to i32
ret i32 %b
@ -38,7 +38,7 @@ define i32 @f3(i64 %x, i64 %y) {
; CHECK-NEXT: rsb r3, r2, #32
; CHECK-NEXT: subs r2, r2, #32
; CHECK-NEXT: orr r0, r0, r1, lsl r3
; CHECK-NEXT: movge r0, r1, lsr r2
; CHECK-NEXT: lsrge r0, r1, r2
%a = lshr i64 %x, %y
%b = trunc i64 %a to i32
ret i32 %b

7
utils/TableGen/ARMDecoderEmitter.cpp
View File

@ -1606,13 +1606,12 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI,
// better off using the generic RSCri and RSCrs instructions.
if (Name == "RSCSri" || Name == "RSCSrs") return false;
// MOVCCr, MOVCCs, MOVCCi, MOVCCi16, FCYPScc, FCYPDcc, FNEGScc, and
// MOVCCi, MOVCCi16, FCYPScc, FCYPDcc, FNEGScc, and
// FNEGDcc are used in the compiler to implement conditional moves.
// We can ignore them in favor of their more generic versions of
// instructions. See also SDNode *ARMDAGToDAGISel::Select(SDValue Op).
if (Name == "MOVCCr" || Name == "MOVCCs" || Name == "MOVCCi" ||
Name == "MOVCCi16" || Name == "FCPYScc" || Name == "FCPYDcc" ||
Name == "FNEGScc" || Name == "FNEGDcc")
if (Name == "MOVCCi" || Name == "MOVCCi16" || Name == "FCPYScc" ||
Name == "FCPYDcc" || Name == "FNEGScc" || Name == "FNEGDcc")
return false;
// Ditto for VMOVDcc, VMOVScc, VNEGDcc, and VNEGScc.