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CONCAT_VECTORS can have more than two operands. PR11389.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144768 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman 2011-11-16 02:52:39 +00:00
parent b91b6001a6
commit d577df8e5a
2 changed files with 21 additions and 22 deletions
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34
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -2926,38 +2926,28 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
DebugLoc dl = N->getDebugLoc();
SDValue Op0 = N->getOperand(0);
SDValue Op1 = N->getOperand(1);
assert(Op0.getValueType() == Op1.getValueType() &&
"Invalid input vector types");
EVT OutVT = N->getValueType(0);
EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
assert(NOutVT.isVector() && "This type must be promoted to a vector type");
EVT InElemTy = OutVT.getVectorElementType();
EVT OutElemTy = NOutVT.getVectorElementType();
unsigned NumElem0 = Op0.getValueType().getVectorNumElements();
unsigned NumElem1 = Op1.getValueType().getVectorNumElements();
unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
unsigned NumOutElem = NOutVT.getVectorNumElements();
assert(NumElem0 + NumElem1 == NumOutElem &&
"Invalid number of incoming elements");
unsigned NumOperands = N->getNumOperands();
assert(NumElem * NumOperands == NumOutElem &&
"Unexpected number of elements");
// Take the elements from the first vector.
SmallVector<SDValue, 8> Ops(NumOutElem);
for (unsigned i = 0; i < NumElem0; ++i) {
SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
Op0.getValueType().getScalarType(), Op0,
DAG.getIntPtrConstant(i));
Ops[i] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
}
// Take the elements from the second vector
for (unsigned i = 0; i < NumElem1; ++i) {
SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
Op1.getValueType().getScalarType(), Op1,
DAG.getIntPtrConstant(i));
Ops[i + NumElem0] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
for (unsigned i = 0; i < NumOperands; ++i) {
SDValue Op = N->getOperand(i);
for (unsigned j = 0; j < NumElem; ++j) {
SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
InElemTy, Op, DAG.getIntPtrConstant(j));
Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
}
}
return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());

9
test/CodeGen/X86/widen_shuffle-1.ll
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@ -54,3 +54,12 @@ define <8 x i8> @shuf4(<4 x i8> %a, <4 x i8> %b) nounwind readnone {
%vshuf = shufflevector <4 x i8> %a, <4 x i8> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i8> %vshuf
}
; PR11389: another CONCAT_VECTORS case
define void @shuf5(<8 x i8>* %p) nounwind {
; CHECK: shuf5:
; CHECK-NOT: punpcklwd
%v = shufflevector <2 x i8> <i8 4, i8 33>, <2 x i8> undef, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
store <8 x i8> %v, <8 x i8>* %p, align 8
ret void
}