RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-12-13 14:46:53 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Add support for the ARM 't' register constraint. And another testcase

Browse Source 
for the 'x' register constraint.

Part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134220 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2011-07-01 00:30:46 +00:00
parent e1bff38386
commit d5dc9eca2b
2 changed files with 25 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -7484,6 +7484,7 @@ ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
case 'w': return C_RegisterClass;
case 'h': return C_RegisterClass;
case 'x': return C_RegisterClass;
case 't': return C_RegisterClass;
}
} else if (Constraint.size() == 2) {
switch (Constraint[0]) {
@ -7563,6 +7564,10 @@ ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
if (VT.getSizeInBits() == 128)
return RCPair(0U, ARM::QPR_8RegisterClass);
break;
case 't':
if (VT == MVT::f32)
return RCPair(0U, ARM::SPRRegisterClass);
break;
}
}
if (StringRef("{cc}").equals_lower(Constraint))

20
test/CodeGen/ARM/inlineasm3.ll
View File

@ -68,3 +68,23 @@ entry:
%0 = tail call float asm "flds s15, $0", "=x"() nounwind
ret float %0
}
; Radar 9307836 & 9119939
define double @t7(double %y) nounwind ssp {
entry:
; CHECK: t7
; CHECK: flds s15, d0
%0 = tail call double asm "flds s15, $0", "=x"() nounwind
ret double %0
}
; Radar 9307836 & 9119939
define float @t8(float %y) nounwind ssp {
entry:
; CHECK: t8
; CHECK: flds s15, s0
%0 = tail call float asm "flds s15, $0", "=t"() nounwind
ret float %0
}