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[MIPS]Multiple and add instructions for Mips are currently available in mips32r2/mips64r2 and later but should also be available in mips4, mips5, and mips64. This patch fixes the requested features and updates the corresponding test files.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230500 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vladimir Medic 2015-02-25 15:24:37 +00:00
parent 51fc7f5afa
commit d692ee81e8
14 changed files with 70 additions and 94 deletions
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28
lib/Target/Mips/MipsInstrFPU.td
View File

@ -458,42 +458,42 @@ def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>;
def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
MADDS_FM<4, 0>, ISA_MIPS32R2_NOT_32R6_64R6;
MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
MADDS_FM<5, 0>, ISA_MIPS32R2_NOT_32R6_64R6;
MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
let AdditionalPredicates = [NoNaNsFPMath] in {
def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
MADDS_FM<6, 0>, ISA_MIPS32R2_NOT_32R6_64R6;
MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
MADDS_FM<7, 0>, ISA_MIPS32R2_NOT_32R6_64R6;
MADDS_FM<7, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
}
def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
MADDS_FM<4, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32;
MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
MADDS_FM<5, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32;
MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
let AdditionalPredicates = [NoNaNsFPMath] in {
def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
MADDS_FM<6, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32;
MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
MADDS_FM<7, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32;
MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
}
let isCodeGenOnly=1 in {
let DecoderNamespace = "Mips64" in {
def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
MADDS_FM<4, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
MADDS_FM<5, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
}
let AdditionalPredicates = [NoNaNsFPMath],
isCodeGenOnly=1 in {
DecoderNamespace = "Mips64" in {
def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
MADDS_FM<6, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>,
MADDS_FM<7, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
}
//===----------------------------------------------------------------------===//

64
test/CodeGen/Mips/fmadd1.ll
View File

@ -39,10 +39,9 @@ entry:
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R6-DAG: add.s $f0, $[[T1]], $[[T2]]
; 64-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
; 64-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $f14
; 64-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 64-DAG: add.s $f0, $[[T1]], $[[T2]]
; 64-DAG: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
; 64-DAG: add.s $f0, $[[T0]], $[[T1]]
; 64R2: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
@ -80,10 +79,9 @@ entry:
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R6-DAG: add.s $f0, $[[T1]], $[[T2]]
; 64-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
; 64-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $f14
; 64-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 64-DAG: add.s $f0, $[[T1]], $[[T2]]
; 64-DAG: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
; 64-DAG: add.s $f0, $[[T0]], $[[T1]]
; 64R2: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
@ -124,10 +122,11 @@ entry:
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R6-DAG: sub.s $f0, $[[T2]], $[[T1]]
; 64-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
; 64-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $f14
; 64-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 64-DAG: sub.s $f0, $[[T2]], $[[T1]]
; 64-NONAN: nmadd.s $f0, $f14, $f12, $f13
; 64-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
; 64-NAN: sub.s $f0, $[[T1]], $[[T0]]
; 64R2-NONAN: nmadd.s $f0, $f14, $f12, $f13
@ -164,10 +163,11 @@ entry:
; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R2-NAN: sub.s $f0, $[[T2]], $[[T1]]
; 64-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
; 64-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $f14
; 64-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 64-DAG: sub.s $f0, $[[T2]], $[[T1]]
; 64-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
; 64-NAN: sub.s $f0, $[[T1]], $[[T0]]
; 64-NONAN: nmsub.s $f0, $f14, $f12, $f13
; 64R2-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
@ -206,10 +206,9 @@ entry:
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R6-DAG: add.d $f0, $[[T1]], $[[T2]]
; 64-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
; 64-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $f14
; 64-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
; 64-DAG: add.d $f0, $[[T1]], $[[T2]]
; 64-DAG: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
; 64-DAG: add.d $f0, $[[T0]], $[[T1]]
; 64R2: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
@ -248,10 +247,9 @@ entry:
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R6-DAG: add.d $f0, $[[T1]], $[[T2]]
; 64-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
; 64-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $f14
; 64-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
; 64-DAG: add.d $f0, $[[T1]], $[[T2]]
; 64-DAG: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
; 64-DAG: add.d $f0, $[[T0]], $[[T1]]
; 64R2: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
@ -293,10 +291,11 @@ entry:
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R6-DAG: sub.d $f0, $[[T2]], $[[T1]]
; 64-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
; 64-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $f14
; 64-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
; 64-DAG: sub.d $f0, $[[T2]], $[[T1]]
; 64-NONAN: nmadd.d $f0, $f14, $f12, $f13
; 64-NAN: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
; 64-NAN: sub.d $f0, $[[T1]], $[[T0]]
; 64R2-NONAN: nmadd.d $f0, $f14, $f12, $f13
@ -340,10 +339,11 @@ entry:
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
; 32R6-DAG: sub.d $f0, $[[T2]], $[[T1]]
; 64-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
; 64-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $f14
; 64-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
; 64-DAG: sub.d $f0, $[[T2]], $[[T1]]
; 64-NONAN: nmsub.d $f0, $f14, $f12, $f13
; 64-NAN: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
; 64-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
; 64-NAN: sub.d $f0, $[[T1]], $[[T0]]
; 64R2-NONAN: nmsub.d $f0, $f14, $f12, $f13

4
test/MC/Mips/mips4/invalid-mips64r2.s
View File

@ -17,19 +17,15 @@
luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
madd $s6,$t5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
madd $zero,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
maddu $t8,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
msubu $t7,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mtc0 $t1,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
seh $v1,$t4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

8
test/MC/Mips/mips4/valid-xfail.s
View File

@ -35,14 +35,6 @@
c.ult.s $fcc7,$f24,$f10
c.un.d $fcc6,$f23,$f24
c.un.s $fcc1,$f30,$f4
madd.d $f18,$f19,$f26,$f20
madd.s $f1,$f31,$f19,$f25
msub.d $f10,$f1,$f31,$f18
msub.s $f12,$f19,$f10,$f16
nmadd.d $f18,$f9,$f14,$f19
nmadd.s $f0,$f5,$f25,$f12
nmsub.d $f30,$f8,$f16,$f30
nmsub.s $f1,$f24,$f19,$f4
recip.d $f19,$f6
recip.s $f3,$f30
rsqrt.d $f3,$f28

8
test/MC/Mips/mips4/valid.s
View File

@ -134,6 +134,8 @@
lwr $zero,-19147($gp)
lwu $s3,-24086($v1)
lwxc1 $f12,$s1($s8)
madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1]
madd.s $f2, $f30, $f18, $f24 # encoding: [0x4f,0xd8,0x90,0xa0]
mfc1 $a3,$f27
mfhi $s3
mfhi $sp
@ -156,6 +158,8 @@
movz $a1,$s6,$9
movz.d $f12,$f29,$9
movz.s $f25,$f7,$v1
msub.d $f10, $f2, $f30, $f18 # encoding: [0x4c,0x52,0xf2,0xa9]
msub.s $f12, $f18, $f10, $f16 # encoding: [0x4e,0x50,0x53,0x28]
mtc1 $s8,$f9
mthi $s1
mtlo $sp
@ -170,6 +174,10 @@
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18
neg.s $f1,$f15
nmadd.d $f18, $f8, $f14, $f20 # encoding: [0x4d,0x14,0x74,0xb1]
nmadd.s $f0, $f4, $f24, $f12 # encoding: [0x4c,0x8c,0xc0,0x30]
nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9]
nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38]
nop
nor $a3,$zero,$a3
or $12,$s0,$sp

4
test/MC/Mips/mips5/invalid-mips64r2.s
View File

@ -21,19 +21,15 @@
ei $14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
maddu $24,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
msubu $15,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mtc0 $9,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
rotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
rotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

8
test/MC/Mips/mips5/valid-xfail.s
View File

@ -57,25 +57,17 @@
cvt.ps.s $f3,$f18,$f19
cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25
madd.d $f18,$f19,$f26,$f20
madd.ps $f22,$f3,$f14,$f3
madd.s $f1,$f31,$f19,$f25
mov.ps $f22,$f17
movf.ps $f10,$f28,$fcc6
movn.ps $f31,$f31,$s3
movt.ps $f20,$f25,$fcc2
movz.ps $f18,$f17,$ra
msub.d $f10,$f1,$f31,$f18
msub.ps $f12,$f14,$f29,$f17
msub.s $f12,$f19,$f10,$f16
mul.ps $f14,$f0,$f16
neg.ps $f19,$f13
nmadd.d $f18,$f9,$f14,$f19
nmadd.ps $f27,$f4,$f9,$f25
nmadd.s $f0,$f5,$f25,$f12
nmsub.d $f30,$f8,$f16,$f30
nmsub.ps $f6,$f12,$f14,$f17
nmsub.s $f1,$f24,$f19,$f4
pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29
pul.ps $f9,$f30,$f26

8
test/MC/Mips/mips5/valid.s
View File

@ -135,6 +135,8 @@
lwr $zero,-19147($gp)
lwu $s3,-24086($v1)
lwxc1 $f12,$s1($s8)
madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1]
madd.s $f2, $f30, $f18, $f24 # encoding: [0x4f,0xd8,0x90,0xa0]
mfc1 $a3,$f27
mfhi $s3
mfhi $sp
@ -157,6 +159,8 @@
movz $a1,$s6,$9
movz.d $f12,$f29,$9
movz.s $f25,$f7,$v1
msub.d $f10, $f2, $f30, $f18 # encoding: [0x4c,0x52,0xf2,0xa9]
msub.s $f12, $f18, $f10, $f16 # encoding: [0x4e,0x50,0x53,0x28]
mtc1 $s8,$f9
mthi $s1
mtlo $sp
@ -171,6 +175,10 @@
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18
neg.s $f1,$f15
nmadd.d $f18, $f8, $f14, $f20 # encoding: [0x4d,0x14,0x74,0xb1]
nmadd.s $f0, $f4, $f24, $f12 # encoding: [0x4c,0x8c,0xc0,0x30]
nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9]
nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38]
nop
nor $a3,$zero,$a3
or $12,$s0,$sp

4
test/MC/Mips/mips64/invalid-mips64r2.s
View File

@ -14,12 +14,8 @@
dsbh $v1,$14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
ei $14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
rotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
rotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

8
test/MC/Mips/mips64/valid-xfail.s
View File

@ -62,9 +62,7 @@
cvt.s.pu $f14,$f25
dmfc0 $10,c0_watchhi,2
dmtc0 $15,c0_datalo
madd.d $f18,$f19,$f26,$f20
madd.ps $f22,$f3,$f14,$f3
madd.s $f1,$f31,$f19,$f25
mov.ps $f22,$f17
movf.ps $f10,$f28,$fcc6
movn.ps $f31,$f31,$s3
@ -72,17 +70,11 @@
movz.ps $f18,$f17,$ra
msgn.qh $v0,$v24,$v20
msgn.qh $v12,$v21,$v0[1]
msub.d $f10,$f1,$f31,$f18
msub.ps $f12,$f14,$f29,$f17
msub.s $f12,$f19,$f10,$f16
mul.ps $f14,$f0,$f16
neg.ps $f19,$f13
nmadd.d $f18,$f9,$f14,$f19
nmadd.ps $f27,$f4,$f9,$f25
nmadd.s $f0,$f5,$f25,$f12
nmsub.d $f30,$f8,$f16,$f30
nmsub.ps $f6,$f12,$f14,$f17
nmsub.s $f1,$f24,$f19,$f4
pll.ps $f25,$f9,$f30
plu.ps $f1,$f26,$f29
pul.ps $f9,$f30,$f26

8
test/MC/Mips/mips64/valid.s
View File

@ -144,6 +144,8 @@
madd $zero,$9
maddu $s3,$gp
maddu $24,$s2
madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1]
madd.s $f2, $f30, $f18, $f24 # encoding: [0x4f,0xd8,0x90,0xa0]
mfc0 $a2,$14,1
mfc1 $a3,$f27
mfhi $s3
@ -169,6 +171,8 @@
movz.s $f25,$f7,$v1
msub $s7,$k1
msubu $15,$a1
msub.d $f10, $f2, $f30, $f18 # encoding: [0x4c,0x52,0xf2,0xa9]
msub.s $f12, $f18, $f10, $f16 # encoding: [0x4e,0x50,0x53,0x28]
mtc0 $9,$29,3
mtc1 $s8,$f9
mthi $s1
@ -185,6 +189,10 @@
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18
neg.s $f1,$f15
nmadd.d $f18, $f8, $f14, $f20 # encoding: [0x4d,0x14,0x74,0xb1]
nmadd.s $f0, $f4, $f24, $f12 # encoding: [0x4c,0x8c,0xc0,0x30]
nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9]
nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38]
nop
nor $a3,$zero,$a3
or $12,$s0,$sp

4
test/MC/Mips/mips64r2/valid-xfail.s
View File

@ -176,7 +176,6 @@
lwle $11,-42($11)
lwre $sp,-152($24)
lwx $12,$12($s4)
madd.d $f18,$f19,$f26,$f20
madd.ps $f22,$f3,$f14,$f3
maq_s.w.phl $ac2,$25,$11
maq_s.w.phr $ac0,$10,$25
@ -193,7 +192,6 @@
msgn.qh $v0,$v24,$v20
msgn.qh $v12,$v21,$v0[1]
msub $ac2,$sp,$14
msub.d $f10,$f1,$f31,$f18
msub.ps $f12,$f14,$f29,$f17
msubu $ac2,$a1,$24
mtc0 $9,c0_datahi1
@ -222,9 +220,7 @@
nlzc.d $w14,$w14
nlzc.h $w24,$w24
nlzc.w $w10,$w4
nmadd.d $f18,$f9,$f14,$f19
nmadd.ps $f27,$f4,$f9,$f25
nmsub.d $f30,$f8,$f16,$f30
nmsub.ps $f6,$f12,$f14,$f17
nor.v $w20,$w20,$w15
or.v $w13,$w23,$w12

4
test/MC/Mips/mips64r3/valid-xfail.s
View File

@ -176,7 +176,6 @@
lwle $11,-42($11)
lwre $sp,-152($24)
lwx $12,$12($s4)
madd.d $f18,$f19,$f26,$f20
madd.ps $f22,$f3,$f14,$f3
maq_s.w.phl $ac2,$25,$11
maq_s.w.phr $ac0,$10,$25
@ -193,7 +192,6 @@
msgn.qh $v0,$v24,$v20
msgn.qh $v12,$v21,$v0[1]
msub $ac2,$sp,$14
msub.d $f10,$f1,$f31,$f18
msub.ps $f12,$f14,$f29,$f17
msubu $ac2,$a1,$24
mtc0 $9,c0_datahi1
@ -222,9 +220,7 @@
nlzc.d $w14,$w14
nlzc.h $w24,$w24
nlzc.w $w10,$w4
nmadd.d $f18,$f9,$f14,$f19
nmadd.ps $f27,$f4,$f9,$f25
nmsub.d $f30,$f8,$f16,$f30
nmsub.ps $f6,$f12,$f14,$f17
nor.v $w20,$w20,$w15
or.v $w13,$w23,$w12

4
test/MC/Mips/mips64r5/valid-xfail.s
View File

@ -176,7 +176,6 @@
lwle $11,-42($11)
lwre $sp,-152($24)
lwx $12,$12($s4)
madd.d $f18,$f19,$f26,$f20
madd.ps $f22,$f3,$f14,$f3
maq_s.w.phl $ac2,$25,$11
maq_s.w.phr $ac0,$10,$25
@ -193,7 +192,6 @@
msgn.qh $v0,$v24,$v20
msgn.qh $v12,$v21,$v0[1]
msub $ac2,$sp,$14
msub.d $f10,$f1,$f31,$f18
msub.ps $f12,$f14,$f29,$f17
msubu $ac2,$a1,$24
mtc0 $9,c0_datahi1
@ -222,9 +220,7 @@
nlzc.d $w14,$w14
nlzc.h $w24,$w24
nlzc.w $w10,$w4
nmadd.d $f18,$f9,$f14,$f19
nmadd.ps $f27,$f4,$f9,$f25
nmsub.d $f30,$f8,$f16,$f30
nmsub.ps $f6,$f12,$f14,$f17
nor.v $w20,$w20,$w15
or.v $w13,$w23,$w12