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Trivial MC code emitter shell. No instruction forms actually handled yet.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115993 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-10-07 22:12:50 +00:00
parent a98111cf15
commit d6d4b42ba4
1 changed files with 19 additions and 3 deletions
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22
lib/Target/ARM/ARMMCCodeEmitter.cpp
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@ -13,13 +13,16 @@
#define DEBUG_TYPE "arm-emitter"
#include "ARM.h"
#include "ARMBaseInfo.h"
#include "ARMInstrInfo.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
namespace {
class ARMMCCodeEmitter : public MCCodeEmitter {
ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
@ -31,7 +34,6 @@ class ARMMCCodeEmitter : public MCCodeEmitter {
public:
ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
: TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
assert(0 && "ARMMCCodeEmitter::ARMMCCodeEmitter() not yet implemented.");
}
~ARMMCCodeEmitter() {}
@ -107,7 +109,21 @@ EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
void ARMMCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const {
assert(0 && "ARMMCCodeEmitter::EncodeInstruction() not yet implemented.");
unsigned Opcode = MI.getOpcode();
const TargetInstrDesc &Desc = TII.get(Opcode);
uint64_t TSFlags = Desc.TSFlags;
// Pseudo instructions don't get encoded.
if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
return;
++MCNumEmitted; // Keep track of the # of mi's emitted
switch (TSFlags & ARMII::FormMask) {
default: {
llvm_unreachable("Unhandled instruction encoding format!");
break;
}
}
}
// FIXME: These #defines shouldn't be necessary. Instead, tblgen should