[AArch64][GlobalISel] Add default regbank mapping for G_FCMP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281738 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/AArch64/AArch64RegisterBankInfo.cpp

@@ -221,6 +221,16 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
       OpBanks[Idx] = AArch64::GPRRegBankID;
   }
 
+  // Some of the floating-point instructions have mixed GPR and FPR operands:
+  // fine-tune the computed mapping.
+  switch (Opc) {
+  case TargetOpcode::G_FCMP: {
+    OpBanks = {AArch64::GPRRegBankID, /* Predicate */ 0, AArch64::FPRRegBankID,
+               AArch64::FPRRegBankID};
+    break;
+  }
+  }
+
   // Finally construct the computed mapping.
   for (unsigned Idx = 0; Idx < MI.getNumOperands(); ++Idx)
     if (MI.getOperand(Idx).isReg())

test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir

@@ -59,6 +59,8 @@
 
   define void @test_fconstant_s32() { ret void }
 
+  define void @test_fcmp_s32() { ret void }
+
 ...
 
 ---
@@ -766,3 +768,22 @@ body: |
     ; CHECK:      %0(s32) = G_FCONSTANT float 1.0
     %0(s32) = G_FCONSTANT float 1.0
 ...
+
+---
+# CHECK-LABEL: name: test_fcmp_s32
+name:            test_fcmp_s32
+legalized:       true
+# CHECK: registers:
+# CHECK:   - { id: 0, class: fpr }
+# CHECK:   - { id: 1, class: gpr }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body: |
+  bb.0:
+    liveins: %s0
+    ; CHECK:      %0(s32) = COPY %s0
+    ; CHECK:      %1(s1) = G_FCMP floatpred(olt), %0(s32), %0
+    %0(s32) = COPY %s0
+    %1(s1) = G_FCMP floatpred(olt), %0, %0
+...