From d7e473c629a5e4fb1584fb5c5c1b0c1e142fdc8f Mon Sep 17 00:00:00 2001 From: Evan Cheng <evan.cheng@apple.com> Date: Fri, 29 Oct 2010 18:07:31 +0000 Subject: [PATCH] - Don't schedule nodes with only MVT::Flag and MVT::Other values for latency. - Compute CopyToReg use operand latency correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117674 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMISelLowering.cpp | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 39f8f05423b..810335b4c57 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -855,6 +855,8 @@ Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const { for (unsigned i = 0; i != NumVals; ++i) { EVT VT = N->getValueType(i); + if (VT == MVT::Flag || VT == MVT::Other) + continue; if (VT.isFloatingPoint() || VT.isVector()) return Sched::Latency; } @@ -866,11 +868,13 @@ Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const { // is not available. const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); const TargetInstrDesc &TID = TII->get(N->getMachineOpcode()); - if (TID.mayLoad()) + + if (TID.getNumDefs() == 0) + return Sched::RegPressure; + if (!Itins->isEmpty() && + Itins->getOperandCycle(TID.getSchedClass(), 0) > 2) return Sched::Latency; - if (!Itins->isEmpty() && Itins->getStageLatency(TID.getSchedClass()) > 2) - return Sched::Latency; return Sched::RegPressure; }