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[GlobalISel] Add G_XOR.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277172 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ahmed Bougacha 2016-07-29 16:56:20 +00:00
parent 8d4e8d2a52
commit d8a8826830
4 changed files with 36 additions and 0 deletions
include/llvm/Target
GenericOpcodes.tdTargetOpcodes.def
lib/CodeGen/GlobalISel
IRTranslator.cpp
test/CodeGen/AArch64/GlobalISel
arm64-irtranslator.ll

8
include/llvm/Target/GenericOpcodes.td

@ -76,6 +76,14 @@ def G_OR : Instruction {
let isCommutable = 1;
}
// Generic bitwise xor.
def G_XOR : Instruction {
let OutOperandList = (outs unknown:$dst);
let InOperandList = (ins unknown:$src1, unknown:$src2);
let hasSideEffects = 0;
let isCommutable = 1;
}
//------------------------------------------------------------------------------
// Memory ops
//------------------------------------------------------------------------------

3
include/llvm/Target/TargetOpcodes.def

@ -168,6 +168,9 @@ HANDLE_TARGET_OPCODE(G_AND)
/// Generic Bitwise-OR instruction.
HANDLE_TARGET_OPCODE(G_OR)
/// Generic Bitwise-OR instruction.
HANDLE_TARGET_OPCODE(G_XOR)
/// Generic instruction to materialize the address of an alloca or other
/// stack-based object.
HANDLE_TARGET_OPCODE(G_FRAME_INDEX)

2
lib/CodeGen/GlobalISel/IRTranslator.cpp

@ -199,6 +199,8 @@ bool IRTranslator::translate(const Instruction &Inst) {
return translateBinaryOp(TargetOpcode::G_AND, Inst);
case Instruction::Or:
return translateBinaryOp(TargetOpcode::G_OR, Inst);
case Instruction::Xor:
return translateBinaryOp(TargetOpcode::G_XOR, Inst);
// Branch operations.
case Instruction::Br:

23
test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

@ -81,6 +81,29 @@ define i32 @ori32(i32 %arg1, i32 %arg2) {
ret i32 %res
}
; Tests for xor.
; CHECK-LABEL: name: xori64
; CHECK: [[ARG1:%[0-9]+]](64) = COPY %x0
; CHECK-NEXT: [[ARG2:%[0-9]+]](64) = COPY %x1
; CHECK-NEXT: [[RES:%[0-9]+]](64) = G_XOR s64 [[ARG1]], [[ARG2]]
; CHECK-NEXT: %x0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit %x0
define i64 @xori64(i64 %arg1, i64 %arg2) {
%res = xor i64 %arg1, %arg2
ret i64 %res
}
; CHECK-LABEL: name: xori32
; CHECK: [[ARG1:%[0-9]+]](32) = COPY %w0
; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %w1
; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_XOR s32 [[ARG1]], [[ARG2]]
; CHECK-NEXT: %w0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit %w0
define i32 @xori32(i32 %arg1, i32 %arg2) {
%res = xor i32 %arg1, %arg2
ret i32 %res
}
; Tests for and.
; CHECK-LABEL: name: andi64
; CHECK: [[ARG1:%[0-9]+]](64) = COPY %x0