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ARM target does not use printAliasInstr machinery which
forces having special checks in ArmInstPrinter::printInstruction. This patch addresses this issue. Not all special checks could be removed: either they involve elaborated conditions under which the alias is emitted (e.g. ldm/stm on sp may be pop/push but only if the number of registers is >= 2) or the number of registers is multivalued (like happens again with ldm/stm) and they do not match the InstAlias pattern which assumes single-valued operands in the pattern. Patch by: Roger Ferrer Ibanez Differential Revision: http://reviews.llvm.org/D20237 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271667 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sjoerd Meijer
parent
d02bd6484d
commit
d8f5dc0ff2
@ -258,20 +258,21 @@ def const_pool_asm_imm : Operand<i32> {
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//===----------------------------------------------------------------------===//
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// ARM Assembler alias templates.
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//
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class ARMInstAlias<string Asm, dag Result, bit Emit = 0b1>
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: InstAlias<Asm, Result, Emit>, Requires<[IsARM]>;
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class tInstAlias<string Asm, dag Result, bit Emit = 0b1>
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: InstAlias<Asm, Result, Emit>, Requires<[IsThumb]>;
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class t2InstAlias<string Asm, dag Result, bit Emit = 0b1>
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: InstAlias<Asm, Result, Emit>, Requires<[IsThumb2]>;
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class VFP2InstAlias<string Asm, dag Result, bit Emit = 0b1>
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: InstAlias<Asm, Result, Emit>, Requires<[HasVFP2]>;
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class VFP2DPInstAlias<string Asm, dag Result, bit Emit = 0b1>
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: InstAlias<Asm, Result, Emit>, Requires<[HasVFP2,HasDPVFP]>;
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class VFP3InstAlias<string Asm, dag Result, bit Emit = 0b1>
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: InstAlias<Asm, Result, Emit>, Requires<[HasVFP3]>;
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class NEONInstAlias<string Asm, dag Result, bit Emit = 0b1>
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: InstAlias<Asm, Result, Emit>, Requires<[HasNEON]>;
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// Note: When EmitPriority == 1, the alias will be used for printing
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class ARMInstAlias<string Asm, dag Result, bit EmitPriority = 0>
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: InstAlias<Asm, Result, EmitPriority>, Requires<[IsARM]>;
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class tInstAlias<string Asm, dag Result, bit EmitPriority = 0>
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: InstAlias<Asm, Result, EmitPriority>, Requires<[IsThumb]>;
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class t2InstAlias<string Asm, dag Result, bit EmitPriority = 0>
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: InstAlias<Asm, Result, EmitPriority>, Requires<[IsThumb2]>;
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class VFP2InstAlias<string Asm, dag Result, bit EmitPriority = 0>
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: InstAlias<Asm, Result, EmitPriority>, Requires<[HasVFP2]>;
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class VFP2DPInstAlias<string Asm, dag Result, bit EmitPriority = 0>
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: InstAlias<Asm, Result, EmitPriority>, Requires<[HasVFP2,HasDPVFP]>;
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class VFP3InstAlias<string Asm, dag Result, bit EmitPriority = 0>
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: InstAlias<Asm, Result, EmitPriority>, Requires<[HasVFP3]>;
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class NEONInstAlias<string Asm, dag Result, bit EmitPriority = 0>
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: InstAlias<Asm, Result, EmitPriority>, Requires<[HasNEON]>;
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class VFP2MnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>,
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@ -2459,22 +2460,25 @@ class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
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}
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// VFP/NEON Instruction aliases for type suffices.
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class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result> :
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InstAlias<!strconcat(opc, dt, "\t", asm), Result>, Requires<[HasVFP2]>;
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// Note: When EmitPriority == 1, the alias will be used for printing
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class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result, bit EmitPriority = 0> :
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InstAlias<!strconcat(opc, dt, "\t", asm), Result, EmitPriority>, Requires<[HasVFP2]>;
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multiclass VFPDTAnyInstAlias<string opc, string asm, dag Result> {
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def : VFPDataTypeInstAlias<opc, ".8", asm, Result>;
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def : VFPDataTypeInstAlias<opc, ".16", asm, Result>;
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def : VFPDataTypeInstAlias<opc, ".32", asm, Result>;
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def : VFPDataTypeInstAlias<opc, ".64", asm, Result>;
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// Note: When EmitPriority == 1, the alias will be used for printing
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multiclass VFPDTAnyInstAlias<string opc, string asm, dag Result, bit EmitPriority = 0> {
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def : VFPDataTypeInstAlias<opc, ".8", asm, Result, EmitPriority>;
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def : VFPDataTypeInstAlias<opc, ".16", asm, Result, EmitPriority>;
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def : VFPDataTypeInstAlias<opc, ".32", asm, Result, EmitPriority>;
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def : VFPDataTypeInstAlias<opc, ".64", asm, Result, EmitPriority>;
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}
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multiclass NEONDTAnyInstAlias<string opc, string asm, dag Result> {
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// Note: When EmitPriority == 1, the alias will be used for printing
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multiclass NEONDTAnyInstAlias<string opc, string asm, dag Result, bit EmitPriority = 0> {
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let Predicates = [HasNEON] in {
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def : VFPDataTypeInstAlias<opc, ".8", asm, Result>;
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def : VFPDataTypeInstAlias<opc, ".16", asm, Result>;
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def : VFPDataTypeInstAlias<opc, ".32", asm, Result>;
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def : VFPDataTypeInstAlias<opc, ".64", asm, Result>;
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def : VFPDataTypeInstAlias<opc, ".8", asm, Result, EmitPriority>;
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def : VFPDataTypeInstAlias<opc, ".16", asm, Result, EmitPriority>;
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def : VFPDataTypeInstAlias<opc, ".32", asm, Result, EmitPriority>;
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def : VFPDataTypeInstAlias<opc, ".64", asm, Result, EmitPriority>;
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}
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}
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@ -1945,7 +1945,7 @@ def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
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let Inst{7-4} = 0b0111;
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}
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// default immediate for breakpoint mnemonic
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def : InstAlias<"bkpt", (BKPT 0)>, Requires<[IsARM]>;
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def : InstAlias<"bkpt", (BKPT 0), 0>, Requires<[IsARM]>;
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def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
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"hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
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@ -3333,7 +3333,7 @@ def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
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}
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def : InstAlias<"mov${p} $Rd, $imm",
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(MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
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(MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p), 0>,
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Requires<[IsARM, HasV6T2]>;
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def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
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@ -5187,7 +5187,7 @@ def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
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let Unpredictable{11-0} = 0b110100001111;
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}
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def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
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def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p), 0>,
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Requires<[IsARM]>;
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// The MRSsys instruction is the MRS instruction from the ARM ARM,
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@ -5593,9 +5593,9 @@ include "ARMInstrNEON.td"
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//
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// Memory barriers
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def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
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def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
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def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
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def : InstAlias<"dmb", (DMB 0xf), 0>, Requires<[IsARM, HasDB]>;
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def : InstAlias<"dsb", (DSB 0xf), 0>, Requires<[IsARM, HasDB]>;
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def : InstAlias<"isb", (ISB 0xf), 0>, Requires<[IsARM, HasDB]>;
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// System instructions
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def : MnemonicAlias<"swi", "svc">;
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@ -5611,10 +5611,10 @@ def : MnemonicAlias<"stmea", "stm">;
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// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the
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// input operands swapped when the shift amount is zero (i.e., unspecified).
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def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
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(PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
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(PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p), 0>,
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Requires<[IsARM, HasV6]>;
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def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
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(PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p)>,
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(PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p), 0>,
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Requires<[IsARM, HasV6]>;
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// PUSH/POP aliases for STM/LDM
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@ -5772,23 +5772,23 @@ def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
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// the instruction definitions need difference constraints pre-v6.
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// Use these aliases for the assembly parsing on pre-v6.
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def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
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(MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
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(MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s), 0>,
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Requires<[IsARM, NoV6]>;
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def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
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(MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
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pred:$p, cc_out:$s)>,
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pred:$p, cc_out:$s), 0>,
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Requires<[IsARM, NoV6]>;
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def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
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(SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
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(SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
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Requires<[IsARM, NoV6]>;
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def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
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(UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
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(UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
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Requires<[IsARM, NoV6]>;
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def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
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(SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
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(SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
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Requires<[IsARM, NoV6]>;
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def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
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(UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
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(UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
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Requires<[IsARM, NoV6]>;
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// 'it' blocks in ARM mode just validate the predicates. The IT itself
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@ -274,16 +274,17 @@ def tHINT : T1pI<(outs), (ins imm0_15:$imm), NoItinerary, "hint", "\t$imm",
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let Inst{7-4} = imm;
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}
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class tHintAlias<string Asm, dag Result> : tInstAlias<Asm, Result> {
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// Note: When EmitPriority == 1, the alias will be used for printing
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class tHintAlias<string Asm, dag Result, bit EmitPriority = 0> : tInstAlias<Asm, Result, EmitPriority> {
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let Predicates = [IsThumb, HasV6M];
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}
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def : tHintAlias<"nop$p", (tHINT 0, pred:$p)>; // A8.6.110
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def : tHintAlias<"yield$p", (tHINT 1, pred:$p)>; // A8.6.410
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def : tHintAlias<"wfe$p", (tHINT 2, pred:$p)>; // A8.6.408
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def : tHintAlias<"wfi$p", (tHINT 3, pred:$p)>; // A8.6.409
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def : tHintAlias<"sev$p", (tHINT 4, pred:$p)>; // A8.6.157
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def : tInstAlias<"sevl$p", (tHINT 5, pred:$p)> {
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def : tHintAlias<"nop$p", (tHINT 0, pred:$p), 1>; // A8.6.110
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def : tHintAlias<"yield$p", (tHINT 1, pred:$p), 1>; // A8.6.410
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def : tHintAlias<"wfe$p", (tHINT 2, pred:$p), 1>; // A8.6.408
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def : tHintAlias<"wfi$p", (tHINT 3, pred:$p), 1>; // A8.6.409
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def : tHintAlias<"sev$p", (tHINT 4, pred:$p), 1>; // A8.6.157
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def : tInstAlias<"sevl$p", (tHINT 5, pred:$p), 1> {
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let Predicates = [IsThumb2, HasV8];
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}
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@ -298,7 +299,7 @@ def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
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let Inst{7-0} = val;
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}
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// default immediate for breakpoint mnemonic
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def : InstAlias<"bkpt", (tBKPT 0)>, Requires<[IsThumb]>;
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def : InstAlias<"bkpt", (tBKPT 0), 0>, Requires<[IsThumb]>;
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def tHLT : T1I<(outs), (ins imm0_63:$val), NoItinerary, "hlt\t$val",
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[]>, T1Encoding<0b101110>, Requires<[IsThumb, HasV8]> {
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@ -784,7 +785,7 @@ def tSTMIA_UPD : Thumb1I<(outs GPR:$wb),
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} // hasSideEffects
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def : InstAlias<"ldm${p} $Rn!, $regs",
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(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
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(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs), 0>,
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Requires<[IsThumb, IsThumb1Only]>;
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let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
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@ -1516,7 +1517,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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// In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00
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// encoding is available on ARMv6K, but we don't differentiate that finely.
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def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>;
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def : InstAlias<"nop", (tMOVr R8, R8, 14, 0), 0>, Requires<[IsThumb, IsThumb1Only]>;
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// For round-trip assembly/disassembly, we have to handle a CPS instruction
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@ -1924,7 +1924,7 @@ def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
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}
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def : InstAlias<"mov${p} $Rd, $imm",
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(t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p)>,
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(t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p), 0>,
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Requires<[IsThumb, HasV8MBaseline]>;
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def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
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@ -1998,7 +1998,7 @@ def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
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def t2UXTH : T2I_ext_rrot<0b001, "uxth",
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UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
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def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
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UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
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UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
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// FIXME: This pattern incorrectly assumes the shl operator is a rotate.
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// The transformation should probably be done as a combiner action
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@ -3720,13 +3720,13 @@ def t2HINT : T2I<(outs), (ins imm0_239:$imm), NoItinerary, "hint", ".w\t$imm",
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let Inst{7-0} = imm;
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}
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def : t2InstAlias<"hint$p $imm", (t2HINT imm0_239:$imm, pred:$p)>;
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def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p)>;
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def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p)>;
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def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p)>;
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def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p)>;
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def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p)>;
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def : t2InstAlias<"sevl$p.w", (t2HINT 5, pred:$p)> {
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def : t2InstAlias<"hint$p $imm", (t2HINT imm0_239:$imm, pred:$p), 0>;
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def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p), 1>;
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def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p), 1>;
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def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p), 1>;
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def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p), 1>;
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def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p), 1>;
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def : t2InstAlias<"sevl$p.w", (t2HINT 5, pred:$p), 1> {
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let Predicates = [IsThumb2, HasV8];
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}
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@ -3853,7 +3853,7 @@ def : t2InstAlias<"hvc\t$imm16", (t2HVC imm0_65535:$imm16)>;
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// ERET - Return from exception in Hypervisor mode.
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// B9.3.3, B9.3.20: ERET is an alias for "SUBS PC, LR, #0" in an implementation that
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// includes virtualization extensions.
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def t2ERET : InstAlias<"eret${p}", (t2SUBS_PC_LR 0, pred:$p)>,
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def t2ERET : InstAlias<"eret${p}", (t2SUBS_PC_LR 0, pred:$p), 1>,
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Requires<[IsThumb2, HasVirtualization]>;
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//===----------------------------------------------------------------------===//
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@ -4527,9 +4527,9 @@ def : t2InstAlias<"tst${p} $Rn, $Rm",
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(t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
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// Memory barriers
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def : InstAlias<"dmb${p}", (t2DMB 0xf, pred:$p)>, Requires<[HasDB]>;
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def : InstAlias<"dsb${p}", (t2DSB 0xf, pred:$p)>, Requires<[HasDB]>;
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def : InstAlias<"isb${p}", (t2ISB 0xf, pred:$p)>, Requires<[HasDB]>;
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def : InstAlias<"dmb${p}", (t2DMB 0xf, pred:$p), 0>, Requires<[HasDB]>;
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def : InstAlias<"dsb${p}", (t2DSB 0xf, pred:$p), 0>, Requires<[HasDB]>;
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def : InstAlias<"isb${p}", (t2ISB 0xf, pred:$p), 0>, Requires<[HasDB]>;
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// Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
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// width specifier.
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@ -4577,10 +4577,10 @@ def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
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// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the
|
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// input operands swapped when the shift amount is zero (i.e., unspecified).
|
||||
def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
|
||||
(t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
|
||||
(t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
|
||||
Requires<[HasT2ExtractPack, IsThumb2]>;
|
||||
def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
|
||||
(t2PKHBT rGPR:$Rd, rGPR:$Rm, rGPR:$Rn, 0, pred:$p)>,
|
||||
(t2PKHBT rGPR:$Rd, rGPR:$Rm, rGPR:$Rn, 0, pred:$p), 0>,
|
||||
Requires<[HasT2ExtractPack, IsThumb2]>;
|
||||
|
||||
// PUSH/POP aliases for STM/LDM
|
||||
@ -4659,16 +4659,16 @@ def : t2InstAlias<"strh${p} $Rt, $addr",
|
||||
|
||||
// Extend instruction optional rotate operand.
|
||||
def : InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
|
||||
(t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
|
||||
(t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
|
||||
Requires<[HasT2ExtractPack, IsThumb2]>;
|
||||
def : InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
|
||||
(t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
|
||||
(t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
|
||||
Requires<[HasT2ExtractPack, IsThumb2]>;
|
||||
def : InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
|
||||
(t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
|
||||
(t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
|
||||
Requires<[HasT2ExtractPack, IsThumb2]>;
|
||||
def : InstAlias<"sxtb16${p} $Rd, $Rm",
|
||||
(t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>,
|
||||
(t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>,
|
||||
Requires<[HasT2ExtractPack, IsThumb2]>;
|
||||
|
||||
def : t2InstAlias<"sxtb${p} $Rd, $Rm",
|
||||
@ -4681,16 +4681,16 @@ def : t2InstAlias<"sxth${p}.w $Rd, $Rm",
|
||||
(t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
|
||||
|
||||
def : InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
|
||||
(t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
|
||||
(t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
|
||||
Requires<[HasT2ExtractPack, IsThumb2]>;
|
||||
def : InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
|
||||
(t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
|
||||
(t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
|
||||
Requires<[HasT2ExtractPack, IsThumb2]>;
|
||||
def : InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
|
||||
(t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
|
||||
(t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
|
||||
Requires<[HasT2ExtractPack, IsThumb2]>;
|
||||
def : InstAlias<"uxtb16${p} $Rd, $Rm",
|
||||
(t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>,
|
||||
(t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>,
|
||||
Requires<[HasT2ExtractPack, IsThumb2]>;
|
||||
|
||||
def : t2InstAlias<"uxtb${p} $Rd, $Rm",
|
||||
@ -4706,7 +4706,7 @@ def : t2InstAlias<"uxth${p}.w $Rd, $Rm",
|
||||
def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
|
||||
(t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
|
||||
def : InstAlias<"uxtb16${p} $Rd, $Rm$rot",
|
||||
(t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>,
|
||||
(t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>,
|
||||
Requires<[HasT2ExtractPack, IsThumb2]>;
|
||||
def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
|
||||
(t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
|
||||
@ -4714,7 +4714,7 @@ def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
|
||||
def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
|
||||
(t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
|
||||
def : InstAlias<"sxtb16${p} $Rd, $Rm$rot",
|
||||
(t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>,
|
||||
(t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>,
|
||||
Requires<[HasT2ExtractPack, IsThumb2]>;
|
||||
def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
|
||||
(t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
|
||||
@ -4812,5 +4812,5 @@ def t2LDRConstPool
|
||||
def : t2InstAlias<"pld${p} $addr",
|
||||
(t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>;
|
||||
def : InstAlias<"pli${p} $addr",
|
||||
(t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p)>,
|
||||
(t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p), 0>,
|
||||
Requires<[IsThumb2,HasV7]>;
|
||||
|
||||
@ -274,13 +274,13 @@ def : VFP2MnemonicAlias<"fstmdbd", "vstmdb">;
|
||||
def : VFP2MnemonicAlias<"fstmead", "vstmia">;
|
||||
def : VFP2MnemonicAlias<"fstmfdd", "vstmdb">;
|
||||
|
||||
def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>,
|
||||
def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r), 0>,
|
||||
Requires<[HasVFP2]>;
|
||||
def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>,
|
||||
def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r), 0>,
|
||||
Requires<[HasVFP2]>;
|
||||
def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>,
|
||||
def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r), 0>,
|
||||
Requires<[HasVFP2]>;
|
||||
def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>,
|
||||
def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r), 0>,
|
||||
Requires<[HasVFP2]>;
|
||||
defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
|
||||
(VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>;
|
||||
@ -890,13 +890,13 @@ multiclass vrint_inst_zrx<string opc, bit op, bit op2, SDPatternOperator node> {
|
||||
}
|
||||
|
||||
def : InstAlias<!strconcat("vrint", opc, "$p.f16.f16\t$Sd, $Sm"),
|
||||
(!cast<Instruction>(NAME#"H") SPR:$Sd, SPR:$Sm, pred:$p)>,
|
||||
(!cast<Instruction>(NAME#"H") SPR:$Sd, SPR:$Sm, pred:$p), 0>,
|
||||
Requires<[HasFullFP16]>;
|
||||
def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"),
|
||||
(!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p)>,
|
||||
(!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p), 0>,
|
||||
Requires<[HasFPARMv8]>;
|
||||
def : InstAlias<!strconcat("vrint", opc, "$p.f64.f64\t$Dd, $Dm"),
|
||||
(!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p)>,
|
||||
(!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p), 0>,
|
||||
Requires<[HasFPARMv8,HasDPVFP]>;
|
||||
}
|
||||
|
||||
@ -931,10 +931,10 @@ multiclass vrint_inst_anpm<string opc, bits<2> rm,
|
||||
}
|
||||
|
||||
def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"),
|
||||
(!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm)>,
|
||||
(!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm), 0>,
|
||||
Requires<[HasFPARMv8]>;
|
||||
def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"),
|
||||
(!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>,
|
||||
(!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm), 0>,
|
||||
Requires<[HasFPARMv8,HasDPVFP]>;
|
||||
}
|
||||
|
||||
|
||||
@ -25,6 +25,7 @@ using namespace llvm;
|
||||
|
||||
#define DEBUG_TYPE "asm-printer"
|
||||
|
||||
#define PRINT_ALIAS_INSTR
|
||||
#include "ARMGenAsmWriter.inc"
|
||||
|
||||
/// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
|
||||
@ -73,43 +74,6 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
|
||||
|
||||
switch (Opcode) {
|
||||
|
||||
// Check for HINT instructions w/ canonical names.
|
||||
case ARM::HINT:
|
||||
case ARM::tHINT:
|
||||
case ARM::t2HINT:
|
||||
switch (MI->getOperand(0).getImm()) {
|
||||
case 0:
|
||||
O << "\tnop";
|
||||
break;
|
||||
case 1:
|
||||
O << "\tyield";
|
||||
break;
|
||||
case 2:
|
||||
O << "\twfe";
|
||||
break;
|
||||
case 3:
|
||||
O << "\twfi";
|
||||
break;
|
||||
case 4:
|
||||
O << "\tsev";
|
||||
break;
|
||||
case 5:
|
||||
if (STI.getFeatureBits()[ARM::HasV8Ops]) {
|
||||
O << "\tsevl";
|
||||
break;
|
||||
} // Fallthrough for non-v8
|
||||
default:
|
||||
// Anything else should just print normally.
|
||||
printInstruction(MI, STI, O);
|
||||
printAnnotation(O, Annot);
|
||||
return;
|
||||
}
|
||||
printPredicateOperand(MI, 1, STI, O);
|
||||
if (Opcode == ARM::t2HINT)
|
||||
O << ".w";
|
||||
printAnnotation(O, Annot);
|
||||
return;
|
||||
|
||||
// Check for MOVs and print canonical forms, instead.
|
||||
case ARM::MOVsr: {
|
||||
// FIXME: Thumb variants?
|
||||
@ -297,23 +261,11 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
|
||||
}
|
||||
break;
|
||||
}
|
||||
// B9.3.3 ERET (Thumb)
|
||||
// For a target that has Virtualization Extensions, ERET is the preferred
|
||||
// disassembly of SUBS PC, LR, #0
|
||||
case ARM::t2SUBS_PC_LR: {
|
||||
if (MI->getNumOperands() == 3 && MI->getOperand(0).isImm() &&
|
||||
MI->getOperand(0).getImm() == 0 &&
|
||||
STI.getFeatureBits()[ARM::FeatureVirtualization]) {
|
||||
O << "\teret";
|
||||
printPredicateOperand(MI, 1, STI, O);
|
||||
printAnnotation(O, Annot);
|
||||
return;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
printInstruction(MI, STI, O);
|
||||
if (!printAliasInstr(MI, STI, O))
|
||||
printInstruction(MI, STI, O);
|
||||
|
||||
printAnnotation(O, Annot);
|
||||
}
|
||||
|
||||
|
||||
@ -30,6 +30,12 @@ public:
|
||||
// Autogenerated by tblgen.
|
||||
void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
|
||||
raw_ostream &O);
|
||||
virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
|
||||
raw_ostream &O);
|
||||
virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
|
||||
unsigned PrintMethodIdx,
|
||||
const MCSubtargetInfo &STI,
|
||||
raw_ostream &O);
|
||||
static const char *getRegisterName(unsigned RegNo);
|
||||
|
||||
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user