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[ARM] Avoid using ARM instructions in Thumb mode
The Requires class overrides the target requirements of an instruction, rather than adding to them, so all ARM instructions need to include the IsARM predicate when they have overwitten requirements. This caused the swp and swpb instructions to be allowed in thumb mode assembly, and the ARM encoding of CDP to be selected in codegen (which is different for conditional instructions). Differential Revision: https://reviews.llvm.org/D29283 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293634 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sam Parker
parent
3bfb126ba5
commit
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@ -74,9 +74,9 @@ public:
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SubtargetFeatures getFeatures() const override;
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SubtargetFeatures getMIPSFeatures() const override;
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SubtargetFeatures getMIPSFeatures() const;
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SubtargetFeatures getARMFeatures() const override;
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SubtargetFeatures getARMFeatures() const;
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void setARMSubArch(Triple &TheTriple) const override;
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};
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@ -267,8 +267,6 @@ public:
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virtual StringRef getFileFormatName() const = 0;
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virtual /* Triple::ArchType */ unsigned getArch() const = 0;
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virtual SubtargetFeatures getFeatures() const = 0;
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virtual SubtargetFeatures getMIPSFeatures() const { return SubtargetFeatures(); }
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virtual SubtargetFeatures getARMFeatures() const { return SubtargetFeatures(); }
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virtual void setARMSubArch(Triple &TheTriple) const { }
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/// Returns platform-specific object flags, if any.
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@ -4831,14 +4831,15 @@ let AddedComplexity = 8 in {
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def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>;
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}
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// SWP/SWPB are deprecated in V6/V7.
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// SWP/SWPB are deprecated in V6/V7 and optional in v7VE.
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// FIXME Use InstAlias to generate LDREX/STREX pairs instead.
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let mayLoad = 1, mayStore = 1 in {
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def SWP : AIswp<0, (outs GPRnopc:$Rt),
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(ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>,
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Requires<[PreV8]>;
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Requires<[IsARM,PreV8]>;
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def SWPB: AIswp<1, (outs GPRnopc:$Rt),
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(ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>,
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Requires<[PreV8]>;
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Requires<[IsARM,PreV8]>;
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}
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//===----------------------------------------------------------------------===//
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@ -4850,7 +4851,7 @@ def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
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NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
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[(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
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imm:$CRm, imm:$opc2)]>,
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Requires<[PreV8]> {
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Requires<[IsARM,PreV8]> {
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bits<4> opc1;
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bits<4> CRn;
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bits<4> CRd;
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@ -4872,7 +4873,7 @@ def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
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NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
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[(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
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imm:$CRm, imm:$opc2)]>,
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Requires<[PreV8]> {
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Requires<[IsARM,PreV8]> {
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let Inst{31-28} = 0b1111;
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bits<4> opc1;
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bits<4> CRn;
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@ -5048,13 +5049,13 @@ multiclass LdSt2Cop<bit load, bit Dbit, string asm, list<dag> pattern> {
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defm LDC : LdStCop <1, 0, "ldc", [(int_arm_ldc imm:$cop, imm:$CRd, addrmode5:$addr)]>;
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defm LDCL : LdStCop <1, 1, "ldcl", [(int_arm_ldcl imm:$cop, imm:$CRd, addrmode5:$addr)]>;
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defm LDC2 : LdSt2Cop<1, 0, "ldc2", [(int_arm_ldc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8]>;
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defm LDC2L : LdSt2Cop<1, 1, "ldc2l", [(int_arm_ldc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8]>;
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defm LDC2 : LdSt2Cop<1, 0, "ldc2", [(int_arm_ldc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>;
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defm LDC2L : LdSt2Cop<1, 1, "ldc2l", [(int_arm_ldc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>;
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defm STC : LdStCop <0, 0, "stc", [(int_arm_stc imm:$cop, imm:$CRd, addrmode5:$addr)]>;
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defm STCL : LdStCop <0, 1, "stcl", [(int_arm_stcl imm:$cop, imm:$CRd, addrmode5:$addr)]>;
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defm STC2 : LdSt2Cop<0, 0, "stc2", [(int_arm_stc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8]>;
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defm STC2L : LdSt2Cop<0, 1, "stc2l", [(int_arm_stc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8]>;
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defm STC2 : LdSt2Cop<0, 0, "stc2", [(int_arm_stc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>;
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defm STC2L : LdSt2Cop<0, 1, "stc2l", [(int_arm_stc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>;
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//===----------------------------------------------------------------------===//
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// Move between coprocessor and ARM core register.
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@ -5132,7 +5133,7 @@ def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
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c_imm:$CRm, imm0_7:$opc2),
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[(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
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imm:$CRm, imm:$opc2)]>,
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Requires<[PreV8]>;
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Requires<[IsARM,PreV8]>;
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def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm",
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(MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
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c_imm:$CRm, 0)>;
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@ -5140,7 +5141,7 @@ def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
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(outs GPRwithAPSR:$Rt),
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(ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
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imm0_7:$opc2), []>,
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Requires<[PreV8]>;
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Requires<[IsARM,PreV8]>;
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def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
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(MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
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c_imm:$CRm, 0)>;
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@ -5183,7 +5184,7 @@ class MovRRCopro2<string opc, bit direction, dag oops, dag iops,
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list<dag> pattern = []>
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: ABXI<0b1100, oops, iops, NoItinerary,
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!strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>,
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Requires<[PreV8]> {
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Requires<[IsARM,PreV8]> {
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let Inst{31-28} = 0b1111;
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let Inst{23-21} = 0b010;
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let Inst{20} = direction;
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@ -1,5 +1,4 @@
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; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
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; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s
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; PR4091
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define void @foo(i32 %i, i32* %p) nounwind {
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@ -1,5 +1,4 @@
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; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 | FileCheck %s
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; RUN: llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 | FileCheck %s
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define void @coproc(i8* %i) nounwind {
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entry:
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93
test/CodeGen/Thumb2/intrinsics-coprocessor.ll
Normal file
93
test/CodeGen/Thumb2/intrinsics-coprocessor.ll
Normal file
@ -0,0 +1,93 @@
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; RUN: llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 -show-mc-encoding | FileCheck %s
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define void @coproc(i8* %i) nounwind {
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entry:
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; CHECK: mrc p7, #1, r{{[0-9]+}}, c1, c1, #4
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%0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
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; CHECK: mcr p7, #1, r{{[0-9]+}}, c1, c1, #4
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tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind
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; CHECK: mrc2 p7, #1, r{{[0-9]+}}, c1, c1, #4
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%1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
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; CHECK: mcr2 p7, #1, r{{[0-9]+}}, c1, c1, #4
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tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind
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; CHECK: mcrr p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c1
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tail call void @llvm.arm.mcrr(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
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; CHECK: mcrr2 p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c1
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tail call void @llvm.arm.mcrr2(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
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; CHECK: cdp p7, #3, c1, c1, c1, #5
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tail call void @llvm.arm.cdp(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
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; CHECK: cdp2 p7, #3, c1, c1, c1, #5
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tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
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; CHECK: ldc p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.ldc(i32 7, i32 3, i8* %i) nounwind
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; CHECK: ldcl p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.ldcl(i32 7, i32 3, i8* %i) nounwind
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; CHECK: ldc2 p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.ldc2(i32 7, i32 3, i8* %i) nounwind
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; CHECK: ldc2l p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.ldc2l(i32 7, i32 3, i8* %i) nounwind
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; CHECK: stc p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.stc(i32 7, i32 3, i8* %i) nounwind
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; CHECK: stcl p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.stcl(i32 7, i32 3, i8* %i) nounwind
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; CHECK: stc2 p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.stc2(i32 7, i32 3, i8* %i) nounwind
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; CHECK: stc2l p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.stc2l(i32 7, i32 3, i8* %i) nounwind
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; CHECK: mrrc p1, #2, r{{[0-9]+}}, r{{[0-9]+}}, c3
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%2 = tail call { i32, i32 } @llvm.arm.mrrc(i32 1, i32 2, i32 3) nounwind
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; CHECK: mrrc2 p1, #2, r{{[0-9]+}}, r{{[0-9]+}}, c3
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%3 = tail call { i32, i32 } @llvm.arm.mrrc2(i32 1, i32 2, i32 3) nounwind
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ret void
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}
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define hidden void @cond_cdp(i32 %a) {
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; CHECK-LABEL: cond_cdp:
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entry:
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%tobool = icmp eq i32 %a, 0
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br i1 %tobool, label %if.end, label %if.then
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if.then:
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; CHECK: it ne
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; CHECK: cdpne p15, #0, c0, c0, c0, #0 @ encoding: [0x00,0xee,0x00,0x0f]
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tail call void @llvm.arm.cdp(i32 15, i32 0, i32 0, i32 0, i32 0, i32 0)
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br label %if.end
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if.end:
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ret void
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}
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declare void @llvm.arm.ldc(i32, i32, i8*) nounwind
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declare void @llvm.arm.ldcl(i32, i32, i8*) nounwind
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declare void @llvm.arm.ldc2(i32, i32, i8*) nounwind
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declare void @llvm.arm.ldc2l(i32, i32, i8*) nounwind
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declare void @llvm.arm.stc(i32, i32, i8*) nounwind
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declare void @llvm.arm.stcl(i32, i32, i8*) nounwind
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declare void @llvm.arm.stc2(i32, i32, i8*) nounwind
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declare void @llvm.arm.stc2l(i32, i32, i8*) nounwind
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declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind
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declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind
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declare void @llvm.arm.mcrr2(i32, i32, i32, i32, i32) nounwind
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declare void @llvm.arm.mcrr(i32, i32, i32, i32, i32) nounwind
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declare void @llvm.arm.mcr2(i32, i32, i32, i32, i32, i32) nounwind
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declare i32 @llvm.arm.mrc2(i32, i32, i32, i32, i32) nounwind
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declare void @llvm.arm.mcr(i32, i32, i32, i32, i32, i32) nounwind
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declare i32 @llvm.arm.mrc(i32, i32, i32, i32, i32) nounwind
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declare { i32, i32 } @llvm.arm.mrrc(i32, i32, i32) nounwind
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declare { i32, i32 } @llvm.arm.mrrc2(i32, i32, i32) nounwind
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@ -117,4 +117,10 @@ foo2:
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: instruction requires: arm-mode
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@ CHECK-ERRORS: error: immediate value expected for vector index
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@ CHECK-ERRORS: error: instruction requires: arm-mode
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@ SWP(B) is an ARM-only instruction
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swp r0, r1, [r2]
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swpb r3, r4, [r5]
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@ CHECK-ERRORS: error: instruction requires: arm-mode
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@ CHECK-ERRORS: error: instruction requires: arm-mode
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