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Enable lowering ZERO_EXTEND/ANY_EXTEND to PMOVZX from SSE4.1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166486 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Michael Liao
parent
bf261f11a0
commit
d9d09600ee
@ -6562,6 +6562,78 @@ SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
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getShuffleSHUFImmediate(SVOp), DAG);
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}
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// Reduce a vector shuffle to zext.
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SDValue
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X86TargetLowering::lowerVectorIntExtend(SDValue Op, SelectionDAG &DAG) const {
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// PMOVZX is only available from SSE41.
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if (!Subtarget->hasSSE41())
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return SDValue();
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EVT VT = Op.getValueType();
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// Only AVX2 support 256-bit vector integer extending.
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if (!Subtarget->hasAVX2() && VT.is256BitVector())
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return SDValue();
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ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
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DebugLoc DL = Op.getDebugLoc();
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SDValue V1 = Op.getOperand(0);
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SDValue V2 = Op.getOperand(1);
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unsigned NumElems = VT.getVectorNumElements();
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// Extending is an unary operation and the element type of the source vector
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// won't be equal to or larger than i64.
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if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
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VT.getVectorElementType() == MVT::i64)
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return SDValue();
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// Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
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unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
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while ((1 << Shift) < NumElems) {
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if (SVOp->getMaskElt(1 << Shift) == 1)
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break;
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Shift += 1;
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// The maximal ratio is 8, i.e. from i8 to i64.
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if (Shift > 3)
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return SDValue();
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}
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// Check the shuffle mask.
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unsigned Mask = (1U << Shift) - 1;
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for (unsigned i = 0; i != NumElems; ++i) {
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int EltIdx = SVOp->getMaskElt(i);
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if ((i & Mask) != 0 && EltIdx != -1)
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return SDValue();
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if ((i & Mask) == 0 && EltIdx != (i >> Shift))
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return SDValue();
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}
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unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
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EVT NeVT = EVT::getIntegerVT(*DAG.getContext(), NBits);
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EVT NVT = EVT::getVectorVT(*DAG.getContext(), NeVT, NumElems >> Shift);
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if (!isTypeLegal(NVT))
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return SDValue();
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// Simplify the operand as it's prepared to be fed into shuffle.
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unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
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if (V1.getOpcode() == ISD::BITCAST &&
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V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
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V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
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V1.getOperand(0)
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.getOperand(0).getValueType().getSizeInBits() == SignificantBits) {
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// (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
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SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
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// If it's foldable, i.e. normal load with single use, we will let code
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// selection to fold it. Otherwise, we will short the conversion sequence.
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if (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())
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V1 = DAG.getNode(ISD::BITCAST, DL, V1.getValueType(), V);
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}
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return DAG.getNode(ISD::BITCAST, DL, VT,
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DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
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}
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SDValue
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X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
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ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
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@ -6592,6 +6664,11 @@ X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
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return PromoteSplat(SVOp, DAG);
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}
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// Check integer expanding shuffles.
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SDValue NewOp = lowerVectorIntExtend(Op, DAG);
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if (NewOp.getNode())
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return NewOp;
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// If the shuffle can be profitably rewritten as a narrower shuffle, then
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// do it!
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if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
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@ -11825,6 +11902,8 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
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case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
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case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
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case X86ISD::VZEXT: return "X86ISD::VZEXT";
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case X86ISD::VSEXT: return "X86ISD::VSEXT";
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case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
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case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
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case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
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@ -16529,6 +16608,21 @@ static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
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return OptimizeConditionalInDecrement(N, DAG);
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}
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/// performVZEXTCombine - Performs build vector combines
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static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget *Subtarget) {
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// (vzext (bitcast (vzext (x)) -> (vzext x)
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SDValue In = N->getOperand(0);
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while (In.getOpcode() == ISD::BITCAST)
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In = In.getOperand(0);
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if (In.getOpcode() != X86ISD::VZEXT)
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return SDValue();
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return DAG.getNode(X86ISD::VZEXT, N->getDebugLoc(), N->getValueType(0), In.getOperand(0));
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}
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SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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@ -16569,6 +16663,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
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case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
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case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
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case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
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case X86ISD::SHUFP: // Handle all target specific shuffles
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case X86ISD::PALIGN:
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case X86ISD::UNPCKH:
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@ -236,6 +236,12 @@ namespace llvm {
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// VSEXT_MOVL - Vector move low and sign extend.
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VSEXT_MOVL,
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// VZEXT - Vector integer zero-extend.
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VZEXT,
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// VSEXT - Vector integer signed-extend.
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VSEXT,
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// VFPEXT - Vector FP extend.
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VFPEXT,
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@ -832,6 +838,8 @@ namespace llvm {
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SDValue LowerVectorAllZeroTest(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerVectorIntExtend(SDValue Op, SelectionDAG &DAG) const;
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virtual SDValue
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LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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@ -90,6 +90,14 @@ def X86vsmovl : SDNode<"X86ISD::VSEXT_MOVL",
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def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
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[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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def X86vzext : SDNode<"X86ISD::VZEXT",
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SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
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SDTCisInt<0>, SDTCisInt<1>]>>;
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def X86vsext : SDNode<"X86ISD::VSEXT",
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SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
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SDTCisInt<0>, SDTCisInt<1>]>>;
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def X86vfpext : SDNode<"X86ISD::VFPEXT",
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SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
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SDTCisFP<0>, SDTCisFP<1>]>>;
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@ -5841,6 +5841,81 @@ let Predicates = [UseSSE41] in {
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(PMOVZXBQrm addr:$src)>;
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}
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let Predicates = [HasAVX2] in {
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def : Pat<(v16i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWYrr VR128:$src)>;
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def : Pat<(v8i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDYrr VR128:$src)>;
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def : Pat<(v4i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQYrr VR128:$src)>;
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def : Pat<(v8i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDYrr VR128:$src)>;
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def : Pat<(v4i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQYrr VR128:$src)>;
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def : Pat<(v4i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQYrr VR128:$src)>;
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}
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let Predicates = [HasAVX] in {
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def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWrr VR128:$src)>;
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def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDrr VR128:$src)>;
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def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQrr VR128:$src)>;
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def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDrr VR128:$src)>;
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def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQrr VR128:$src)>;
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def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQrr VR128:$src)>;
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def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
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(VPMOVZXBWrm addr:$src)>;
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def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
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(VPMOVZXBWrm addr:$src)>;
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def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
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(VPMOVZXBDrm addr:$src)>;
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def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
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(VPMOVZXBQrm addr:$src)>;
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def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
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(VPMOVZXWDrm addr:$src)>;
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def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
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(VPMOVZXWDrm addr:$src)>;
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def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
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(VPMOVZXWQrm addr:$src)>;
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def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
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(VPMOVZXDQrm addr:$src)>;
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def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
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(VPMOVZXDQrm addr:$src)>;
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}
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let Predicates = [UseSSE41] in {
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def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (PMOVZXBWrr VR128:$src)>;
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def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (PMOVZXBDrr VR128:$src)>;
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def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (PMOVZXBQrr VR128:$src)>;
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def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (PMOVZXWDrr VR128:$src)>;
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def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (PMOVZXWQrr VR128:$src)>;
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def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (PMOVZXDQrr VR128:$src)>;
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def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
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(PMOVZXBWrm addr:$src)>;
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def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
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(PMOVZXBWrm addr:$src)>;
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def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
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(PMOVZXBDrm addr:$src)>;
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def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
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(PMOVZXBQrm addr:$src)>;
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def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
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(PMOVZXWDrm addr:$src)>;
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def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
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(PMOVZXWDrm addr:$src)>;
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def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
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(PMOVZXWQrm addr:$src)>;
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def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
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(PMOVZXDQrm addr:$src)>;
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def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
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(PMOVZXDQrm addr:$src)>;
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}
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//===----------------------------------------------------------------------===//
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// SSE4.1 - Extract Instructions
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//===----------------------------------------------------------------------===//
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@ -2,8 +2,8 @@
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;CHECK: vcast
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define <2 x i32> @vcast(<2 x float> %a, <2 x float> %b) {
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;CHECK: pshufd
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;CHECK: pshufd
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;CHECK: pmovzxdq
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;CHECK: pmovzxdq
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%af = bitcast <2 x float> %a to <2 x i32>
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%bf = bitcast <2 x float> %b to <2 x i32>
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%x = sub <2 x i32> %af, %bf
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@ -4,7 +4,7 @@
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define <4 x i8> @build_vector_again(<16 x i8> %in) nounwind readnone {
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entry:
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%out = shufflevector <16 x i8> %in, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK: shufb
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; CHECK: pmovzxbd
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ret <4 x i8> %out
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; CHECK: ret
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}
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@ -3,7 +3,7 @@
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; CHECK: load_store
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define void @load_store(<4 x i16>* %in) {
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entry:
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; CHECK: movsd
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; CHECK: pmovzxwd
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%A27 = load <4 x i16>* %in, align 4
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%A28 = add <4 x i16> %A27, %A27
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; CHECK: movlpd
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@ -27,6 +27,6 @@ define <2 x i32> @load_64(<2 x i32>* %ptr) {
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BB:
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%t = load <2 x i32>* %ptr
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ret <2 x i32> %t
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;CHECK: movsd
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;CHECK: pmovzxdq
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;CHECK: ret
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}
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@ -81,8 +81,7 @@ define <4 x i32*> @INT2PTR1(<4 x i8>* %p) nounwind {
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entry:
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%G = load <4 x i8>* %p
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;CHECK: movl
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;CHECK: movd
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;CHECK: pshufb
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;CHECK: pmovzxbd
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;CHECK: pand
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%K = inttoptr <4 x i8> %G to <4 x i32*>
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;CHECK: ret
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@ -105,7 +104,7 @@ define <2 x i32*> @BITCAST1(<2 x i8*>* %p) nounwind {
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entry:
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%G = load <2 x i8*>* %p
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;CHECK: movl
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;CHECK: movsd
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;CHECK: pmovzxdq
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%T = bitcast <2 x i8*> %G to <2 x i32*>
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;CHECK: ret
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ret <2 x i32*> %T
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@ -20,7 +20,7 @@ entry:
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; CHECK: shuff_f
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define i32 @shuff_f(<4 x i8>* %A) {
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entry:
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; CHECK: pshufb
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; CHECK: pmovzxbd
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; CHECK: paddd
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; CHECK: pshufb
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%0 = load <4 x i8>* %A, align 8
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@ -2,8 +2,7 @@
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;CHECK: load_2_i8
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; A single 16-bit load
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;CHECK: movzwl
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;CHECK: pshufb
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;CHECK: pmovzxbq
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;CHECK: paddq
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;CHECK: pshufb
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; A single 16-bit store
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@ -19,8 +18,7 @@ define void @load_2_i8(<2 x i8>* %A) {
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;CHECK: load_2_i16
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; Read 32-bits
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;CHECK: movd
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;CHECK: pshufb
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;CHECK: pmovzxwq
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;CHECK: paddq
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;CHECK: pshufb
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;CHECK: movd
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@ -33,7 +31,7 @@ define void @load_2_i16(<2 x i16>* %A) {
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}
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;CHECK: load_2_i32
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;CHECK: pshufd
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;CHECK: pmovzxdq
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;CHECK: paddq
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;CHECK: pshufd
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;CHECK: ret
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@ -45,8 +43,7 @@ define void @load_2_i32(<2 x i32>* %A) {
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}
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;CHECK: load_4_i8
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;CHECK: movd
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;CHECK: pshufb
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;CHECK: pmovzxbd
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||||
;CHECK: paddd
|
||||
;CHECK: pshufb
|
||||
;CHECK: ret
|
||||
@ -58,7 +55,7 @@ define void @load_4_i8(<4 x i8>* %A) {
|
||||
}
|
||||
|
||||
;CHECK: load_4_i16
|
||||
;CHECK: punpcklwd
|
||||
;CHECK: pmovzxwd
|
||||
;CHECK: paddd
|
||||
;CHECK: pshufb
|
||||
;CHECK: ret
|
||||
@ -70,7 +67,7 @@ define void @load_4_i16(<4 x i16>* %A) {
|
||||
}
|
||||
|
||||
;CHECK: load_8_i8
|
||||
;CHECK: punpcklbw
|
||||
;CHECK: pmovzxbw
|
||||
;CHECK: paddw
|
||||
;CHECK: pshufb
|
||||
;CHECK: ret
|
||||
|
||||
@ -10,8 +10,7 @@ define void @blackDespeckle_wrapper(i8** %args_list, i64* %gtid, i64 %xend) {
|
||||
entry:
|
||||
; CHECK: cfi_def_cfa_offset
|
||||
; CHECK-NOT: set
|
||||
; CHECK: punpcklwd
|
||||
; CHECK: pshufd
|
||||
; CHECK: pmovzxwq
|
||||
; CHECK: pshufb
|
||||
%shr.i = ashr <4 x i32> zeroinitializer, <i32 3, i32 3, i32 3, i32 3> ; <<4 x i32>> [#uses=1]
|
||||
%cmp318.i = sext <4 x i1> zeroinitializer to <4 x i32> ; <<4 x i32>> [#uses=1]
|
||||
|
||||
@ -170,7 +170,7 @@ define void @add31i8(%i8vec31* nocapture sret %ret, %i8vec31* %ap, %i8vec31* %bp
|
||||
; CHECK: rot
|
||||
%i8vec3pack = type { <3 x i8>, i8 }
|
||||
define %i8vec3pack @rot() nounwind {
|
||||
; CHECK: movd {{-?[0-9]+}}(%rsp), {{%xmm[0-9]}}
|
||||
; CHECK: pmovzxbd {{-?[0-9]+}}(%rsp), {{%xmm[0-9]}}
|
||||
entry:
|
||||
%X = alloca %i8vec3pack, align 4
|
||||
%rot = alloca %i8vec3pack, align 4
|
||||
|
||||
Loading…
Reference in New Issue
Block a user