From d9f01d8662f6217101a7dcdfd256a311d72159fd Mon Sep 17 00:00:00 2001
From: Tim Northover <tnorthover@apple.com>
Date: Mon, 31 Oct 2016 18:31:09 +0000
Subject: [PATCH] GlobalISel: allow truncating pointer casts on AArch64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285615 91177308-0d34-0410-b5e6-96231b3b80d8
---
 .../AArch64/AArch64InstructionSelector.cpp    |  2 +-
 lib/Target/AArch64/AArch64LegalizerInfo.cpp   |  4 +++-
 .../GlobalISel/arm64-instructionselect.mir    | 21 +++++++++++++++++--
 3 files changed, 23 insertions(+), 4 deletions(-)

diff --git a/lib/Target/AArch64/AArch64InstructionSelector.cpp b/lib/Target/AArch64/AArch64InstructionSelector.cpp
index c5777598b65..0dd725ea1d1 100644
--- a/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ b/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -748,6 +748,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
     return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
   }
 
+  case TargetOpcode::G_PTRTOINT:
   case TargetOpcode::G_TRUNC: {
     const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
     const LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
@@ -918,7 +919,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
 
 
   case TargetOpcode::G_INTTOPTR:
-  case TargetOpcode::G_PTRTOINT:
   case TargetOpcode::G_BITCAST:
     return selectCopy(I, TII, MRI, TRI, RBI);
 
diff --git a/lib/Target/AArch64/AArch64LegalizerInfo.cpp b/lib/Target/AArch64/AArch64LegalizerInfo.cpp
index b8f1136b23b..83f276a8161 100644
--- a/lib/Target/AArch64/AArch64LegalizerInfo.cpp
+++ b/lib/Target/AArch64/AArch64LegalizerInfo.cpp
@@ -169,7 +169,9 @@ AArch64LegalizerInfo::AArch64LegalizerInfo() {
   setAction({G_FRAME_INDEX, p0}, Legal);
   setAction({G_GLOBAL_VALUE, p0}, Legal);
 
-  setAction({G_PTRTOINT, 0, s64}, Legal);
+  for (auto Ty : {s1, s8, s16, s32, s64})
+    setAction({G_PTRTOINT, 0, Ty}, Legal);
+
   setAction({G_PTRTOINT, 1, p0}, Legal);
 
   setAction({G_INTTOPTR, 0, p0}, Legal);
diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir b/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
index a86c0659610..b91cc7c2b7b 100644
--- a/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
+++ b/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
@@ -2522,25 +2522,42 @@ regBankSelected: true
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr64all }
 # CHECK-NEXT:  - { id: 1, class: fpr64 }
-# CHECK-NEXT:  - { id: 2, class: gpr64all }
-# CHECK-NEXT:  - { id: 3, class: gpr64all }
+# CHECK-NEXT:  - { id: 2, class: gpr64 }
+# CHECK-NEXT:  - { id: 3, class: gpr64 }
+# CHECK-NEXT:  - { id: 4, class: gpr32 }
+# CHECK-NEXT:  - { id: 5, class: gpr32 }
+# CHECK-NEXT:  - { id: 6, class: gpr32 }
+# CHECK-NEXT:  - { id: 7, class: gpr32 }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+  - { id: 7, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %1 = COPY %0
 # CHECK:    %2 = COPY %0
 # CHECK:    %3 = COPY %2
+# CHECK:    %4 = COPY %2.sub_32
+# CHECK:    %5 = COPY %2.sub_32
+# CHECK:    %6 = COPY %2.sub_32
+# CHECK:    %7 = COPY %2.sub_32
 body:             |
   bb.0:
     liveins: %x0
     %0(s64) = COPY %x0
     %1(<8 x s8>) = G_BITCAST %0(s64)
     %2(p0) = G_INTTOPTR %0
+
     %3(s64) = G_PTRTOINT %2
+    %4(s32) = G_PTRTOINT %2
+    %5(s16) = G_PTRTOINT %2
+    %6(s8) = G_PTRTOINT %2
+    %7(s1) = G_PTRTOINT %2
 ...
 
 ---