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[mips] Do not reserve all 64-bit registers, but only the ones which need to be

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reserved. Without this fix, RegScavenger::getRegsAvailable incorrectly
returns an empty set of integer registers.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167335 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-11-02 23:36:01 +00:00
parent 78c796e203
commit da15a0ed4c
1 changed files with 4 additions and 8 deletions
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12
lib/Target/Mips/MipsRegisterInfo.cpp
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@ -94,20 +94,16 @@ getReservedRegs(const MachineFunction &MF) const {
for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I)
Reserved.set(ReservedCPURegs[I]);
if (Subtarget.hasMips64()) {
for (unsigned I = 0; I < array_lengthof(ReservedCPU64Regs); ++I)
Reserved.set(ReservedCPU64Regs[I]);
for (unsigned I = 0; I < array_lengthof(ReservedCPU64Regs); ++I)
Reserved.set(ReservedCPU64Regs[I]);
if (Subtarget.hasMips64()) {
// Reserve all registers in AFGR64.
for (RegIter Reg = Mips::AFGR64RegClass.begin(),
EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
Reserved.set(*Reg);
} else {
// Reserve all registers in CPU64Regs & FGR64.
for (RegIter Reg = Mips::CPU64RegsRegClass.begin(),
EReg = Mips::CPU64RegsRegClass.end(); Reg != EReg; ++Reg)
Reserved.set(*Reg);
// Reserve all registers in FGR64.
for (RegIter Reg = Mips::FGR64RegClass.begin(),
EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
Reserved.set(*Reg);