Expose the number of Newton-Raphson iterations applied to the hardware's reciprocal estimate as a parameter (x86).

This is a follow-on to r221706 and r221731 and discussed in more detail in PR21385.

This patch also loosens the testcase checking for btver2. We know that the "1.0" will be loaded, but
we can't tell exactly when, so replace the CHECK-NEXT specifiers with plain CHECKs. The CHECK-NEXT
sequence relied on a quirk of post-RA-scheduling that may change independently of anything in these tests.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221819 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sanjay Patel 2014-11-12 21:39:01 +00:00
parent f9e1e56ea1
commit dab91bcc3a
2 changed files with 56 additions and 15 deletions

View File

@ -71,6 +71,12 @@ static cl::opt<bool> ExperimentalVectorShuffleLowering(
cl::desc("Enable an experimental vector shuffle lowering code path."), cl::desc("Enable an experimental vector shuffle lowering code path."),
cl::Hidden); cl::Hidden);
static cl::opt<int> ReciprocalEstimateRefinementSteps(
"x86-recip-refinement-steps", cl::init(1),
cl::desc("Specify the number of Newton-Raphson iterations applied to the "
"result of the hardware reciprocal estimate instruction."),
cl::NotHidden);
// Forward declarations. // Forward declarations.
static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1, static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
SDValue V2); SDValue V2);
@ -14543,9 +14549,7 @@ SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
// along with FMA, this could be a throughput win. // along with FMA, this could be a throughput win.
if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) || if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
(Subtarget->hasAVX() && VT == MVT::v8f32)) { (Subtarget->hasAVX() && VT == MVT::v8f32)) {
// TODO: Expose this as a user-configurable parameter to allow for RefinementSteps = ReciprocalEstimateRefinementSteps;
// speed vs. accuracy flexibility.
RefinementSteps = 1;
return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op); return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
} }
return SDValue(); return SDValue();

View File

@ -1,5 +1,6 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=core2 | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=core2 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=btver2 | FileCheck %s --check-prefix=BTVER2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=btver2 | FileCheck %s --check-prefix=BTVER2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+use-recip-est,+avx -x86-recip-refinement-steps=2 | FileCheck %s --check-prefix=REFINE
; If the target's divss/divps instructions are substantially ; If the target's divss/divps instructions are substantially
; slower than rcpss/rcpps with a Newton-Raphson refinement, ; slower than rcpss/rcpps with a Newton-Raphson refinement,
@ -21,11 +22,23 @@ define float @reciprocal_estimate(float %x) #0 {
; BTVER2-LABEL: reciprocal_estimate: ; BTVER2-LABEL: reciprocal_estimate:
; BTVER2: vrcpss ; BTVER2: vrcpss
; BTVER2-NEXT: vmulss ; BTVER2: vmulss
; BTVER2-NEXT: vsubss ; BTVER2: vsubss
; BTVER2-NEXT: vmulss ; BTVER2: vmulss
; BTVER2-NEXT: vaddss ; BTVER2: vaddss
; BTVER2-NEXT: retq ; BTVER2-NEXT: retq
; REFINE-LABEL: reciprocal_estimate:
; REFINE: vrcpss
; REFINE: vmulss
; REFINE: vsubss
; REFINE: vmulss
; REFINE: vaddss
; REFINE: vmulss
; REFINE: vsubss
; REFINE: vmulss
; REFINE: vaddss
; REFINE-NEXT: retq
} }
define <4 x float> @reciprocal_estimate_v4f32(<4 x float> %x) #0 { define <4 x float> @reciprocal_estimate_v4f32(<4 x float> %x) #0 {
@ -40,11 +53,23 @@ define <4 x float> @reciprocal_estimate_v4f32(<4 x float> %x) #0 {
; BTVER2-LABEL: reciprocal_estimate_v4f32: ; BTVER2-LABEL: reciprocal_estimate_v4f32:
; BTVER2: vrcpps ; BTVER2: vrcpps
; BTVER2-NEXT: vmulps ; BTVER2: vmulps
; BTVER2-NEXT: vsubps ; BTVER2: vsubps
; BTVER2-NEXT: vmulps ; BTVER2: vmulps
; BTVER2-NEXT: vaddps ; BTVER2: vaddps
; BTVER2-NEXT: retq ; BTVER2-NEXT: retq
; REFINE-LABEL: reciprocal_estimate_v4f32:
; REFINE: vrcpps
; REFINE: vmulps
; REFINE: vsubps
; REFINE: vmulps
; REFINE: vaddps
; REFINE: vmulps
; REFINE: vsubps
; REFINE: vmulps
; REFINE: vaddps
; REFINE-NEXT: retq
} }
define <8 x float> @reciprocal_estimate_v8f32(<8 x float> %x) #0 { define <8 x float> @reciprocal_estimate_v8f32(<8 x float> %x) #0 {
@ -62,11 +87,23 @@ define <8 x float> @reciprocal_estimate_v8f32(<8 x float> %x) #0 {
; BTVER2-LABEL: reciprocal_estimate_v8f32: ; BTVER2-LABEL: reciprocal_estimate_v8f32:
; BTVER2: vrcpps ; BTVER2: vrcpps
; BTVER2-NEXT: vmulps ; BTVER2: vmulps
; BTVER2-NEXT: vsubps ; BTVER2: vsubps
; BTVER2-NEXT: vmulps ; BTVER2: vmulps
; BTVER2-NEXT: vaddps ; BTVER2: vaddps
; BTVER2-NEXT: retq ; BTVER2-NEXT: retq
; REFINE-LABEL: reciprocal_estimate_v8f32:
; REFINE: vrcpps
; REFINE: vmulps
; REFINE: vsubps
; REFINE: vmulps
; REFINE: vaddps
; REFINE: vmulps
; REFINE: vsubps
; REFINE: vmulps
; REFINE: vaddps
; REFINE-NEXT: retq
} }
attributes #0 = { "unsafe-fp-math"="true" } attributes #0 = { "unsafe-fp-math"="true" }