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Reapply r274829 with fix for FP vectors

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274937 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2016-07-08 21:25:33 +00:00
parent 532fc83a7f
commit db12f54967
4 changed files with 60 additions and 2 deletions
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6
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -12407,8 +12407,10 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
// This only really matters if the index is non-constant since other combines
// on the constant elements already work.
if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT &&
EltNo == InVec.getOperand(2))
return InVec.getOperand(1);
EltNo == InVec.getOperand(2)) {
SDValue Elt = InVec.getOperand(1);
return VT.isInteger() ? DAG.getAnyExtOrTrunc(Elt, SDLoc(N), NVT) : Elt;
}
// Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
// We only perform this optimization before the op legalization phase because

18
test/CodeGen/AMDGPU/vector-extract-insert.ll
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@ -61,6 +61,24 @@ define void @extract_insert_same_elt2_v4i32(i32 addrspace(1)* %out, <4 x i32> ad
ret void
}
; GCN-LABEL: {{^}}extract_insert_same_dynelt_v4f32:
; GCN: s_load_dword [[VAL:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd{{$}}
; GCN-NOT buffer_load_dword
; GCN-NOT: [[VAL]]
; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
; GCN-NOT: [[VVAL]]
; GCN: buffer_store_dword [[VVAL]]
define void @extract_insert_same_dynelt_v4f32(float addrspace(1)* %out, <4 x float> addrspace(1)* %in, float %val, i32 %idx) #1 {
%id = call i32 @llvm.amdgcn.workitem.id.x()
%id.ext = sext i32 %id to i64
%gep.in = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %in, i64 %id.ext
%gep.out = getelementptr inbounds float, float addrspace(1)* %out, i64 %id.ext
%vec = load volatile <4 x float>, <4 x float> addrspace(1)* %gep.in
%insert = insertelement <4 x float> %vec, float %val, i32 %idx
%extract = extractelement <4 x float> %insert, i32 %idx
store float %extract, float addrspace(1)* %gep.out
ret void
}
attributes #0 = { nounwind readnone }
attributes #1 = { nounwind }

27
test/CodeGen/X86/pr28444.ll Normal file
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@ -0,0 +1,27 @@
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 < %s | FileCheck %s
; https://llvm.org/bugs/show_bug.cgi?id=28444
; extract_vector_elt is allowed to have a different result type than
; the vector scalar type.
; This uses both
; i8 = extract_vector_elt v1i1, Constant:i64<0>
; i1 = extract_vector_elt v1i1, Constant:i64<0>
; CHECK-LABEL: {{^}}extractelt_mismatch_vector_element_type:
; CHECK: movb $1, %al
; CHECK: movb %al
; CHECK: movb %al
define void @extractelt_mismatch_vector_element_type(i32 %arg) {
bb:
%tmp = icmp ult i32 %arg, 0
%tmp2 = insertelement <1 x i1> undef, i1 true, i32 0
%tmp3 = select i1 %tmp, <1 x i1> undef, <1 x i1> %tmp2
%tmp6 = extractelement <1 x i1> %tmp3, i32 0
br label %bb1
bb1:
store volatile <1 x i1> %tmp3, <1 x i1>* undef
store volatile i1 %tmp6, i1* undef
ret void
}

11
test/CodeGen/X86/pr28472.ll Normal file
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@ -0,0 +1,11 @@
; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
; CHECK-LABEL: {{^}}same_dynamic_index_fp_vector_type:
; CHECK: # BB#0:
; CHECK-NEXT: retq
define float @same_dynamic_index_fp_vector_type(float %val, i32 %idx) {
bb:
%tmp0 = insertelement <4 x float> undef, float %val, i32 %idx
%tmp1 = extractelement <4 x float> %tmp0, i32 %idx
ret float %tmp1
}