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The PowerPCInstrInfo class has gone away.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15853 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2004-08-17 05:00:46 +00:00
parent 363dd07320
commit db50bd3e7a
1 changed files with 0 additions and 34 deletions
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34
lib/Target/PowerPC/PowerPCInstrInfo.h
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@ -15,7 +15,6 @@
#define POWERPC_INSTRUCTIONINFO_H
#include "PowerPC.h"
#include "PowerPCRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
namespace llvm {
@ -62,39 +61,6 @@ namespace PPCII {
};
}
class PowerPCInstrInfo : public TargetInstrInfo {
const PowerPCRegisterInfo RI;
bool is64bit;
public:
PowerPCInstrInfo(bool is64b);
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
//
// Return true if the instruction is a register to register move and
// leave the source and dest operands in the passed parameters.
//
virtual bool isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg) const;
static unsigned invertPPCBranchOpcode(unsigned Opcode) {
switch (Opcode) {
default: assert(0 && "Unknown PPC branch opcode!");
case PPC::BEQ: return PPC::BNE;
case PPC::BNE: return PPC::BEQ;
case PPC::BLT: return PPC::BGE;
case PPC::BGE: return PPC::BLT;
case PPC::BGT: return PPC::BLE;
case PPC::BLE: return PPC::BGT;
}
}
};
}
#endif