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Revert r141569 and r141576.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141594 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Devang Patel
parent
f6c35c59f5
commit
db7334dbc5
@ -168,11 +168,6 @@ namespace {
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///
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bool IsLoopInvariantInst(MachineInstr &I);
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/// IsGuaranteedToExecute - check to make sure that the MI dominates
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/// all of the exit blocks. If it doesn't, then there is a path out of the
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/// loop which does not execute this instruction, so we can't hoist it.
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bool IsGuaranteedToExecute(MachineInstr *MI);
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/// HasAnyPHIUse - Return true if the specified register is used by any
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/// phi node.
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bool HasAnyPHIUse(unsigned Reg) const;
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@ -1134,28 +1129,6 @@ bool MachineLICM::EliminateCSE(MachineInstr *MI,
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return false;
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}
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/// IsGuaranteedToExecute - check to make sure that the instruction dominates
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/// all of the exit blocks. If it doesn't, then there is a path out of the loop
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/// which does not execute this instruction, so we can't hoist it.
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bool MachineLICM::IsGuaranteedToExecute(MachineInstr *MI) {
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// If the instruction is in the header block for the loop (which is very
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// common), it is always guaranteed to dominate the exit blocks. Since this
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// is a common case, and can save some work, check it now.
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if (MI->getParent() == CurLoop->getHeader())
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return true;
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// Get the exit blocks for the current loop.
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SmallVector<MachineBasicBlock*, 8> ExitingBlocks;
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CurLoop->getExitingBlocks(ExitingBlocks);
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// Verify that the block dominates each of the exit blocks of the loop.
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for (unsigned i = 0, e = ExitingBlocks.size(); i != e; ++i)
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if (!DT->dominates(MI->getParent(), ExitingBlocks[i]))
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return false;
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return true;
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}
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/// Hoist - When an instruction is found to use only loop invariant operands
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/// that are safe to hoist, this instruction is called to do the dirty work.
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///
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@ -1166,8 +1139,6 @@ bool MachineLICM::Hoist(MachineInstr *MI, MachineBasicBlock *Preheader) {
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MI = ExtractHoistableLoad(MI);
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if (!MI) return false;
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}
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if (!IsGuaranteedToExecute(MI))
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return false;
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// Now move the instructions to the predecessor, inserting it before any
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// terminator instructions.
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@ -4,11 +4,12 @@
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; register pressure and therefore spilling. There is more room for improvement
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; here.
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; CHECK: sub sp, #{{40|32|28|24}}
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; CHECK: sub sp, #{{32|28|24}}
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; CHECK: %for.inc
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; CHECK: ldr{{(.w)?}} r{{.*}}, [sp, #
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; CHECK: ldr{{(.w)?}} r{{.*}}, [sp, #
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; CHECK: ldr{{(.w)?}} r{{.*}}, [sp, #
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; CHECK: add
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target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
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@ -1,56 +0,0 @@
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; RUN: llc < %s | FileCheck %s
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; MachineLICM should check dominance before hoisting instructions.
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; CHECK: xorb %cl, %cl
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; CHECK-NEXT: testb %cl, %cl
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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target triple = "x86_64-apple-macosx10.7.2"
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define void @CMSColorWorldCreateParametricData() nounwind uwtable optsize ssp {
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entry:
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br label %for.body.i
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for.body.i: ; preds = %entry
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br i1 undef, label %for.inc.i, label %land.lhs.true21.i
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land.lhs.true21.i: ; preds = %for.body.i
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br i1 undef, label %if.then26.i, label %for.inc.i
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if.then26.i: ; preds = %land.lhs.true21.i
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br i1 undef, label %if.else.i.i, label %if.then.i.i
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if.then.i.i: ; preds = %if.then26.i
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unreachable
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if.else.i.i: ; preds = %if.then26.i
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br i1 undef, label %lor.lhs.false.i.i, label %if.then116.i.i
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lor.lhs.false.i.i: ; preds = %if.else.i.i
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br i1 undef, label %lor.lhs.false104.i.i, label %if.then116.i.i
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lor.lhs.false104.i.i: ; preds = %lor.lhs.false.i.i
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br i1 undef, label %lor.lhs.false108.i.i, label %if.then116.i.i
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lor.lhs.false108.i.i: ; preds = %lor.lhs.false104.i.i
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br i1 undef, label %lor.lhs.false112.i.i, label %if.then116.i.i
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lor.lhs.false112.i.i: ; preds = %lor.lhs.false108.i.i
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br i1 undef, label %if.else232.i.i, label %if.then116.i.i
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if.then116.i.i: ; preds = %lor.lhs.false112.i.i, %lor.lhs.false108.i.i, %lor.lhs.false104.i.i, %lor.lhs.false.i.i, %if.else.i.i
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unreachable
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if.else232.i.i: ; preds = %lor.lhs.false112.i.i
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br label %for.inc.i
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for.inc.i: ; preds = %if.else232.i.i, %land.lhs.true21.i, %for.body.i
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%cmp17.i = icmp ult i64 undef, undef
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br i1 %cmp17.i, label %for.body.i, label %if.end28.i
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if.end28.i: ; preds = %for.inc.i, %if.then10.i, %if.then6.i
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unreachable
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createTransformParams.exit: ; preds = %land.lhs.true3.i, %if.then.i, %land.lhs.true.i, %entry
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ret void
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}
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@ -1,4 +1,4 @@
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; RUN: llc -mtriple=x86_64-apple-darwin -march=x86-64 < %s -o /dev/null -stats -info-output-file - | grep machine-licm | grep 2
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; RUN: llc -mtriple=x86_64-apple-darwin -march=x86-64 < %s -o /dev/null -stats -info-output-file - | grep machine-licm | grep 3
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; MachineLICM should be able to hoist the symbolic addresses out of
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; the inner loops.
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@ -84,6 +84,65 @@ return:
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; ret i8 %b_addr.0
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; }
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; Codegen should hoist and CSE these constants.
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; CHECK: vv:
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; CHECK: LCPI3_0(%rip), %xmm0
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; CHECK: LCPI3_1(%rip), %xmm1
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; CHECK: LCPI3_2(%rip), %xmm2
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; CHECK: align
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; CHECK-NOT: LCPI
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; CHECK: ret
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@_minusZero.6007 = internal constant <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00> ; <<4 x float>*> [#uses=0]
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@twoTo23.6008 = internal constant <4 x float> <float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06> ; <<4 x float>*> [#uses=0]
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define void @vv(float* %y, float* %x, i32* %n) nounwind ssp {
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entry:
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br label %bb60
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bb: ; preds = %bb60
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%0 = bitcast float* %x_addr.0 to <4 x float>* ; <<4 x float>*> [#uses=1]
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%1 = load <4 x float>* %0, align 16 ; <<4 x float>> [#uses=4]
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%tmp20 = bitcast <4 x float> %1 to <4 x i32> ; <<4 x i32>> [#uses=1]
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%tmp22 = and <4 x i32> %tmp20, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> ; <<4 x i32>> [#uses=1]
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%tmp23 = bitcast <4 x i32> %tmp22 to <4 x float> ; <<4 x float>> [#uses=1]
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%tmp25 = bitcast <4 x float> %1 to <4 x i32> ; <<4 x i32>> [#uses=1]
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%tmp27 = and <4 x i32> %tmp25, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> ; <<4 x i32>> [#uses=2]
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%tmp30 = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %tmp23, <4 x float> <float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06>, i8 5) ; <<4 x float>> [#uses=1]
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%tmp34 = bitcast <4 x float> %tmp30 to <4 x i32> ; <<4 x i32>> [#uses=1]
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%tmp36 = xor <4 x i32> %tmp34, <i32 -1, i32 -1, i32 -1, i32 -1> ; <<4 x i32>> [#uses=1]
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%tmp37 = and <4 x i32> %tmp36, <i32 1258291200, i32 1258291200, i32 1258291200, i32 1258291200> ; <<4 x i32>> [#uses=1]
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%tmp42 = or <4 x i32> %tmp37, %tmp27 ; <<4 x i32>> [#uses=1]
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%tmp43 = bitcast <4 x i32> %tmp42 to <4 x float> ; <<4 x float>> [#uses=2]
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%tmp45 = fadd <4 x float> %1, %tmp43 ; <<4 x float>> [#uses=1]
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%tmp47 = fsub <4 x float> %tmp45, %tmp43 ; <<4 x float>> [#uses=2]
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%tmp49 = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %1, <4 x float> %tmp47, i8 1) ; <<4 x float>> [#uses=1]
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%2 = bitcast <4 x float> %tmp49 to <4 x i32> ; <<4 x i32>> [#uses=1]
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%3 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %2) nounwind readnone ; <<4 x float>> [#uses=1]
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%tmp53 = fadd <4 x float> %tmp47, %3 ; <<4 x float>> [#uses=1]
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%tmp55 = bitcast <4 x float> %tmp53 to <4 x i32> ; <<4 x i32>> [#uses=1]
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%tmp57 = or <4 x i32> %tmp55, %tmp27 ; <<4 x i32>> [#uses=1]
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%tmp58 = bitcast <4 x i32> %tmp57 to <4 x float> ; <<4 x float>> [#uses=1]
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%4 = bitcast float* %y_addr.0 to <4 x float>* ; <<4 x float>*> [#uses=1]
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store <4 x float> %tmp58, <4 x float>* %4, align 16
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%5 = getelementptr float* %x_addr.0, i64 4 ; <float*> [#uses=1]
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%6 = getelementptr float* %y_addr.0, i64 4 ; <float*> [#uses=1]
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%7 = add i32 %i.0, 4 ; <i32> [#uses=1]
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br label %bb60
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bb60: ; preds = %bb, %entry
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%i.0 = phi i32 [ 0, %entry ], [ %7, %bb ] ; <i32> [#uses=2]
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%x_addr.0 = phi float* [ %x, %entry ], [ %5, %bb ] ; <float*> [#uses=2]
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%y_addr.0 = phi float* [ %y, %entry ], [ %6, %bb ] ; <float*> [#uses=2]
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%8 = load i32* %n, align 4 ; <i32> [#uses=1]
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%9 = icmp sgt i32 %8, %i.0 ; <i1> [#uses=1]
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br i1 %9, label %bb, label %return
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return: ; preds = %bb60
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ret void
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}
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declare <4 x float> @llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, i8) nounwind readnone
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declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone
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@ -1,6 +1,5 @@
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; RUN: llc < %s -march=x86-64 -mattr=+sse42 | FileCheck %s
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; CHECK: psubw
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; CHECK-NEXT: movdqa
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; CHECK-NEXT: pmullw
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; Widen a v5i16 to v8i16 to do a vector sub and multiple
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