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[X86] Remove many operands that represent memory stores from outs to ins. These operands are the registers and immediates that specify the memory address not the memory itself thus they are inputs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263354 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
fdae897487
commit
db96b37522
@ -326,7 +326,7 @@ def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">;
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def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">;
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def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">;
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def FSTENVm : FPI<0xD9, MRM6m, (outs f32mem:$dst), (ins), "fnstenv\t$dst">;
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def FSTENVm : FPI<0xD9, MRM6m, (outs), (ins f32mem:$dst), "fnstenv\t$dst">;
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def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">;
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def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">;
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@ -334,15 +334,15 @@ def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">;
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def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">;
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def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">;
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def FRSTORm : FPI<0xDD, MRM4m, (outs f32mem:$dst), (ins), "frstor\t$dst">;
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def FSAVEm : FPI<0xDD, MRM6m, (outs f32mem:$dst), (ins), "fnsave\t$dst">;
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def FNSTSWm : FPI<0xDD, MRM7m, (outs i16mem:$dst), (ins), "fnstsw\t$dst">;
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def FRSTORm : FPI<0xDD, MRM4m, (outs), (ins f32mem:$dst), "frstor\t$dst">;
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def FSAVEm : FPI<0xDD, MRM6m, (outs), (ins f32mem:$dst), "fnsave\t$dst">;
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def FNSTSWm : FPI<0xDD, MRM7m, (outs), (ins i16mem:$dst), "fnstsw\t$dst">;
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def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">;
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def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">;
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def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f80mem:$src), "fbld\t$src">;
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def FBSTPm : FPI<0xDF, MRM6m, (outs f80mem:$dst), (ins), "fbstp\t$dst">;
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def FBSTPm : FPI<0xDF, MRM6m, (outs), (ins f80mem:$dst), "fbstp\t$dst">;
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// Floating point cmovs.
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class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
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@ -1446,30 +1446,30 @@ def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src),
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}
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let mayStore = 1 in {
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let Uses = [AL] in
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def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs offset32_8:$dst), (ins),
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def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs), (ins offset32_8:$dst),
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"mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize32;
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let Uses = [AX] in
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def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_16:$dst), (ins),
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def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs), (ins offset32_16:$dst),
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"mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
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OpSize16, AdSize32;
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let Uses = [EAX] in
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def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_32:$dst), (ins),
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def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs), (ins offset32_32:$dst),
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"mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
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OpSize32, AdSize32;
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let Uses = [RAX] in
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def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs offset32_64:$dst), (ins),
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def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs), (ins offset32_64:$dst),
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"mov{q}\t{%rax, $dst|$dst, rax}", [], IIC_MOV_MEM>,
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AdSize32;
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let Uses = [AL] in
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def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs offset16_8:$dst), (ins),
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def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs), (ins offset16_8:$dst),
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"mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize16;
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let Uses = [AX] in
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def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_16:$dst), (ins),
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def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs), (ins offset16_16:$dst),
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"mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
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OpSize16, AdSize16;
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let Uses = [EAX] in
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def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_32:$dst), (ins),
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def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs), (ins offset16_32:$dst),
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"mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
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OpSize32, AdSize16;
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}
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@ -1995,11 +1995,11 @@ def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src),
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// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
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let Defs = [EDI], Uses = [DX,EDI,EFLAGS] in {
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def INSB : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins),
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def INSB : I<0x6C, RawFrmDst, (outs), (ins dstidx8:$dst),
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"insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;
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def INSW : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins),
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def INSW : I<0x6D, RawFrmDst, (outs), (ins dstidx16:$dst),
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"insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16;
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def INSL : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins),
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def INSL : I<0x6D, RawFrmDst, (outs), (ins dstidx32:$dst),
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"ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32;
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}
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}
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@ -282,7 +282,7 @@ def MMX_MOVQ64rr_REV : MMXI<0x7F, MRMDestReg, (outs VR64:$dst), (ins VR64:$src),
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let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
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def MMX_MOVD64from64rm : MMXRI<0x7E, MRMDestMem,
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(outs i64mem:$dst), (ins VR64:$src),
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(outs), (ins i64mem:$dst, VR64:$src),
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"movd\t{$src, $dst|$dst, $src}",
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[], IIC_MMX_MOV_REG_MM>, Sched<[WriteStore]>;
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@ -55,10 +55,10 @@ def BNDMOVRM64rm : RI<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i128mem:$src),
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def BNDMOVMRrr : I<0x1B, MRMDestReg, (outs BNDR:$dst), (ins BNDR:$src),
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"bndmov\t{$src, $dst|$dst, $src}", []>, PD,
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Requires<[HasMPX]>;
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def BNDMOVMR32mr : I<0x1B, MRMDestMem, (outs i64mem:$dst), (ins BNDR:$src),
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def BNDMOVMR32mr : I<0x1B, MRMDestMem, (outs), (ins i64mem:$dst, BNDR:$src),
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"bndmov\t{$src, $dst|$dst, $src}", []>, PD,
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Requires<[HasMPX, Not64BitMode]>;
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def BNDMOVMR64mr : RI<0x1B, MRMDestMem, (outs i128mem:$dst), (ins BNDR:$src),
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def BNDMOVMR64mr : RI<0x1B, MRMDestMem, (outs), (ins i128mem:$dst, BNDR:$src),
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"bndmov\t{$src, $dst|$dst, $src}", []>, PD,
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Requires<[HasMPX, In64BitMode]>;
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@ -174,11 +174,11 @@ def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
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def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
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def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
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def MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src),
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"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize16;
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def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
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def MOV32ms : I<0x8C, MRMDestMem, (outs), (ins i32mem:$dst, SEGMENT_REG:$src),
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"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize32;
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def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
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def MOV64ms : RI<0x8C, MRMDestMem, (outs), (ins i64mem:$dst, SEGMENT_REG:$src),
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"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>;
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def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
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@ -248,7 +248,7 @@ def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
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"str{l}\t$dst", [], IIC_STR>, TB, OpSize32;
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def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
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"str{q}\t$dst", [], IIC_STR>, TB;
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def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
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def STRm : I<0x00, MRM1m, (outs), (ins i16mem:$dst),
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"str{w}\t$dst", [], IIC_STR>, TB;
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def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
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@ -389,21 +389,21 @@ def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
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// Descriptor-table support instructions
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let SchedRW = [WriteSystem] in {
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def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
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def SGDT16m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst),
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"sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
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def SGDT32m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
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def SGDT32m : I<0x01, MRM0m, (outs), (ins opaque48mem:$dst),
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"sgdt{l}\t$dst", [], IIC_SGDT>, OpSize32, TB, Requires <[Not64BitMode]>;
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def SGDT64m : I<0x01, MRM0m, (outs opaque80mem:$dst), (ins),
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def SGDT64m : I<0x01, MRM0m, (outs), (ins opaque80mem:$dst),
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"sgdt{q}\t$dst", [], IIC_SGDT>, TB, Requires <[In64BitMode]>;
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def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
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def SIDT16m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst),
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"sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
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def SIDT32m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
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def SIDT32m : I<0x01, MRM1m, (outs), (ins opaque48mem:$dst),
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"sidt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
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def SIDT64m : I<0x01, MRM1m, (outs opaque80mem:$dst), (ins),
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def SIDT64m : I<0x01, MRM1m, (outs), (ins opaque80mem:$dst),
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"sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
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def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
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"sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize16;
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def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
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def SLDT16m : I<0x00, MRM0m, (outs), (ins i16mem:$dst),
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"sldt{w}\t$dst", [], IIC_SLDT>, TB;
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def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
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"sldt{l}\t$dst", [], IIC_SLDT>, OpSize32, TB;
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@ -412,7 +412,7 @@ def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
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// extension.
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def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
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"sldt{q}\t$dst", [], IIC_SLDT>, TB;
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def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
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def SLDT64m : RI<0x00, MRM0m, (outs), (ins i16mem:$dst),
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"sldt{q}\t$dst", [], IIC_SLDT>, TB;
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def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
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@ -454,7 +454,7 @@ def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
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"smsw{q}\t$dst", [], IIC_SMSW>, TB;
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// For memory operands, there is only a 16-bit form
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def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
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def SMSW16m : I<0x01, MRM4m, (outs), (ins i16mem:$dst),
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"smsw{w}\t$dst", [], IIC_SMSW>, TB;
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def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
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@ -41,13 +41,13 @@ def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
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def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
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def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
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"vmptrld\t$vmcs", []>, PS;
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def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
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def VMPTRSTm : I<0xC7, MRM7m, (outs), (ins i64mem:$vmcs),
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"vmptrst\t$vmcs", []>, TB;
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def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
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def VMREAD64rm : I<0x78, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
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"vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>;
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def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
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"vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>;
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def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
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def VMREAD32rm : I<0x78, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
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"vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>;
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def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
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"vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>;
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