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[mips] interAptiv based generic schedule model
This scheduler describes a processor which covers all MIPS ISAs based around the interAptiv and P5600 timings. Reviewers: vkalintiris, dsanders Differential Revision: https://reviews.llvm.org/D23551 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280374 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Dardis
parent
0f970f8cb2
commit
dbc69646c5
@ -789,7 +789,7 @@ class MTC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"mtc1", FGR32Opnd, GPR32Opnd,
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class MTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mtc2", COP2Opnd, GPR32Opnd,
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II_MTC2>;
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class MTHC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mthc0", COP0Opnd, GPR32Opnd,
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II_MTC0>;
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II_MTHC0>;
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class MTHC1_D32_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", AFGR64Opnd,
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GPR32Opnd, II_MTC1>,
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HARDFLOAT, FGR_32;
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@ -838,7 +838,7 @@ class MFC1_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfc1", GPR32Opnd, FGR32Opnd,
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class MFC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfc2", GPR32Opnd, COP2Opnd,
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II_MFC2>;
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class MFHC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfhc0", GPR32Opnd, COP0Opnd,
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II_MFC0>;
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II_MFHC0>;
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class MFHC1_D32_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, AFGR64Opnd,
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II_MFHC1>, HARDFLOAT, FGR_32;
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class MFHC1_D64_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, FGR64Opnd,
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@ -59,6 +59,7 @@ include "MipsCallingConv.td"
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// Avoid forward declaration issues.
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include "MipsScheduleP5600.td"
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include "MipsScheduleGeneric.td"
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def MipsInstrInfo : InstrInfo;
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@ -191,7 +192,7 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
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"The P5600 Processor", [FeatureMips32r5]>;
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, MipsGenericItineraries, Features>;
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: ProcessorModel<Name, MipsGenericModel, Features>;
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def : Proc<"mips1", [FeatureMips1]>;
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def : Proc<"mips2", [FeatureMips2]>;
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@ -216,6 +216,7 @@ def II_MIN_S : InstrItinClass;
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def II_MINA_D : InstrItinClass;
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def II_MINA_S : InstrItinClass;
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def II_MFC0 : InstrItinClass;
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def II_MFHC0 : InstrItinClass;
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def II_MFC1 : InstrItinClass;
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def II_MFHC1 : InstrItinClass;
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def II_MFC2 : InstrItinClass;
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@ -244,6 +245,7 @@ def II_MSUB_S : InstrItinClass;
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def II_MSUBF_D : InstrItinClass;
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def II_MSUBF_S : InstrItinClass;
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def II_MTC0 : InstrItinClass;
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def II_MTHC0 : InstrItinClass;
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def II_MTC1 : InstrItinClass;
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def II_MTHC1 : InstrItinClass;
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def II_MTC2 : InstrItinClass;
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@ -640,9 +642,11 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
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InstrItinData<II_DMTC1 , [InstrStage<2, [ALU]>]>,
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InstrItinData<II_DMTC2 , [InstrStage<2, [ALU]>]>,
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InstrItinData<II_MFC0 , [InstrStage<2, [ALU]>]>,
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InstrItinData<II_MFHC0 , [InstrStage<2, [ALU]>]>,
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InstrItinData<II_MFC1 , [InstrStage<2, [ALU]>]>,
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InstrItinData<II_MFC2 , [InstrStage<2, [ALU]>]>,
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InstrItinData<II_MTC0 , [InstrStage<2, [ALU]>]>,
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InstrItinData<II_MTHC0 , [InstrStage<2, [ALU]>]>,
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InstrItinData<II_MTC1 , [InstrStage<2, [ALU]>]>,
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InstrItinData<II_MTC2 , [InstrStage<2, [ALU]>]>,
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InstrItinData<II_MFHC1 , [InstrStage<2, [ALU]>]>,
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@ -15,12 +15,12 @@ entry:
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; O32: lw ${{[0-9]+}}, %call_lo(foo0)($[[R3]])
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; N64-LABEL: foo1:
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; N64: lui $[[R0:[0-9]+]], %got_hi(v0)
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; N64: daddu $[[R1:[0-9]+]], $[[R0]], ${{[a-z0-9]+}}
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; N64: lui $[[R2:[0-9]+]], %call_hi(foo0)
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; N64: daddu $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
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; N64: ld ${{[0-9]+}}, %got_lo(v0)($[[R1]])
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; N64: ld ${{[0-9]+}}, %call_lo(foo0)($[[R3]])
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; N64-DAG: lui $[[R0:[0-9]+]], %got_hi(v0)
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; N64-DAG: daddu $[[R1:[0-9]+]], $[[R0]], ${{[a-z0-9]+}}
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; N64-DAG: lui $[[R2:[0-9]+]], %call_hi(foo0)
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; N64-DAG: daddu $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
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; N64-DAG: ld ${{[0-9]+}}, %got_lo(v0)($[[R1]])
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; N64-DAG: ld ${{[0-9]+}}, %call_lo(foo0)($[[R3]])
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%0 = load i32, i32* @v0, align 4
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tail call void @foo0(i32 %0) nounwind
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@ -152,20 +152,20 @@ entry:
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; ACC64: mfhi $[[R0:[0-9]+]]
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; ACC64: sw $[[R0]], 0(${{[0-9]+}})
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; GPR32-DAG: div $2, $4, $5
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; GPR32-TRAP: teq $5, $zero, 7
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; NOCHECK-NOT: teq
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; GPR32-DAG: mod $[[R0:[0-9]+]], $4, $5
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; GPR32-TRAP: teq $5, $zero, 7
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; GPR32: sw $[[R0]], 0(${{[0-9]+}})
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; GPR64-DAG: div $2, $4, $5
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; GPR64-TRAP: teq $5, $zero, 7
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; NOCHECK-NOT: teq
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; GPR32: sw $[[R0]], 0(${{[0-9]+}})
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; GPR32-DAG: div $2, $4, $5
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; GPR32-TRAP: teq $5, $zero, 7
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; GPR64-DAG: mod $[[R0:[0-9]+]], $4, $5
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; GPR64-TRAP: teq $5, $zero, 7
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; NOCHECK-NOT: teq
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; GPR64: sw $[[R0]], 0(${{[0-9]+}})
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; GPR64-DAG: div $2, $4, $5
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; GPR64-TRAP: teq $5, $zero, 7
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; NOCHECK-NOT: teq
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; ALL: .end sdivrem1
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@ -193,21 +193,21 @@ entry:
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; ACC64: mfhi $[[R0:[0-9]+]]
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; ACC64: sw $[[R0]], 0(${{[0-9]+}})
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; GPR32-DAG: modu $[[R0:[0-9]+]], $4, $5
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; GPR32-TRAP: teq $5, $zero, 7
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; GPR32: sw $[[R0]], 0(${{[0-9]+}})
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; NOCHECK-NOT: teq
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; GPR32-DAG: divu $2, $4, $5
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; GPR32-TRAP: teq $5, $zero, 7
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; NOCHECK-NOT: teq
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; GPR32-DAG: modu $[[R0:[0-9]+]], $4, $5
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; GPR32-TRAP: teq $5, $zero, 7
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; NOCHECK-NOT: teq
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; GPR32: sw $[[R0]], 0(${{[0-9]+}})
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; GPR64-DAG: divu $2, $4, $5
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; GPR64-TRAP: teq $5, $zero, 7
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; NOCHECK-NOT: teq
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; GPR64-DAG: modu $[[R0:[0-9]+]], $4, $5
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; GPR64-TRAP: teq $5, $zero, 7
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; NOCHECK-NOT: teq
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; GPR64: sw $[[R0]], 0(${{[0-9]+}})
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; GPR64-DAG: divu $2, $4, $5
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; GPR64-TRAP: teq $5, $zero, 7
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; NOCHECK-NOT: teq
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; ALL: .end udivrem1
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@ -335,15 +335,15 @@ entry:
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; ACC64: mfhi $[[R0:[0-9]+]]
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; ACC64: sd $[[R0]], 0(${{[0-9]+}})
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; GPR64-DAG: ddiv $2, $4, $5
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; GPR64-TRAP: teq $5, $zero, 7
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; NOCHECK-NOT: teq
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; GPR64-DAG: dmod $[[R0:[0-9]+]], $4, $5
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; GPR64-TRAP: teq $5, $zero, 7
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; NOCHECK-NOT: teq
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; GPR64: sd $[[R0]], 0(${{[0-9]+}})
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; GPR64-DAG: ddiv $2, $4, $5
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; GPR64-TRAP: teq $5, $zero, 7
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; NOCHECK-NOT: teq
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; ALL: .end sdivrem2
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%rem = srem i64 %a0, %a1
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@ -370,15 +370,15 @@ entry:
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; ACC64: mfhi $[[R0:[0-9]+]]
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; ACC64: sd $[[R0]], 0(${{[0-9]+}})
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; GPR64-DAG: ddivu $2, $4, $5
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; GPR64-TRAP: teq $5, $zero, 7
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; NOCHECK-NOT: teq
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; GPR64: dmodu $[[R0:[0-9]+]], $4, $5
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; GPR64-TRAP: teq $5, $zero, 7
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; NOCHECK-NOT: teq
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; GPR64: sd $[[R0]], 0(${{[0-9]+}})
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; GPR64-DAG: ddivu $2, $4, $5
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; GPR64-TRAP: teq $5, $zero, 7
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; NOCHECK-NOT: teq
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; ALL: .end udivrem2
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%rem = urem i64 %a0, %a1
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@ -36,14 +36,14 @@ define double @func3(double %d, float %f) nounwind readnone {
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entry:
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; ALL-LABEL: func3:
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; 64-DAG: mfc1 $[[MFC:[0-9]+]], $f13
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; 64-DAG: srl $[[SRL:[0-9]+]], $[[MFC:[0-9]+]], 31
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; 64: dsll $[[DSLL:[0-9]+]], $[[SRL]], 63
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; 64-DAG: daddiu $[[R1:[0-9]+]], $zero, 1
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; 64-DAG: dsll $[[R2:[0-9]+]], $[[R1]], 63
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; 64-DAG: daddiu $[[R3:[0-9]+]], $[[R2]], -1
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; 64-DAG: dmfc1 $[[R0:[0-9]+]], ${{.*}}
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; 64: dmfc1 $[[R0:[0-9]+]], ${{.*}}
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; 64: daddiu $[[R1:[0-9]+]], $zero, 1
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; 64: dsll $[[R2:[0-9]+]], $[[R1]], 63
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; 64: daddiu $[[R3:[0-9]+]], $[[R2]], -1
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; 64: and $[[AND0:[0-9]+]], $[[R0]], $[[R3]]
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; 64: mfc1 $[[MFC:[0-9]+]], $f13
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; 64: srl $[[SRL:[0-9]+]], $[[MFC:[0-9]+]], 31
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; 64: dsll $[[DSLL:[0-9]+]], $[[SRL]], 63
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; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]]
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; 64: dmtc1 $[[OR]], $f0
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@ -132,13 +132,13 @@ entry:
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; GP32: lw $[[T3:[0-9]+]], 24($sp)
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; GP32: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]]
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; GP32: addu $[[T5:[0-9]+]], $6, $[[T4]]
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; GP32: lw $[[T6:[0-9]+]], 16($sp)
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; GP32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]]
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; GP32: lw $[[T7:[0-9]+]], 20($sp)
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; GP32: sltu $[[T8:[0-9]+]], $[[T5]], $[[T3]]
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; GP32: addu $[[T9:[0-9]+]], $[[T8]], $[[T7]]
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; GP32: addu $[[T8:[0-9]+]], $[[T6]], $[[T7]]
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; GP32: lw $[[T9:[0-9]+]], 16($sp)
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; GP32: addu $3, $5, $[[T8]]
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; GP32: sltu $[[T10:[0-9]+]], $3, $[[T7]]
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; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T6]]
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; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T9]]
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; GP32: addu $2, $4, $[[T11]]
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; GP32: move $4, $[[T5]]
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; GP32: move $5, $[[T1]]
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@ -154,13 +154,13 @@ entry:
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; MM32: lw $[[T3:[0-9]+]], 24($sp)
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; MM32: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]]
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; MM32: addu $[[T5:[0-9]+]], $6, $[[T4]]
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; MM32: lw $[[T6:[0-9]+]], 16($sp)
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; MM32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]]
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; MM32: lw $[[T7:[0-9]+]], 20($sp)
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; MM32: sltu $[[T8:[0-9]+]], $[[T5]], $[[T3]]
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; MM32: addu $[[T9:[0-9]+]], $[[T8]], $[[T7]]
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; MM32: addu $[[T10:[0-9]+]], $5, $[[T9]]
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; MM32: sltu $[[T11:[0-6]+]], $[[T9]], $[[T7]]
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; MM32: addu $[[T12:[0-6]+]], $[[T11]], $[[T6]]
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; MM32: addu $[[T8:[0-9]+]], $[[T6]], $[[T7]]
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; MM32: lw $[[T9:[0-9]+]], 16($sp)
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; MM32: addu $[[T10:[0-9]+]], $5, $[[T8]]
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; MM32: sltu $[[T11:[0-9]+]], $[[T10]], $[[T7]]
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; MM32: addu $[[T12:[0-9]+]], $[[T11]], $[[T9]]
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; MM32: addu $[[T13:[0-9]+]], $4, $[[T12]]
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; MM32: move $4, $[[T5]]
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; MM32: move $5, $[[T1]]
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@ -119,25 +119,25 @@ define signext i128 @and_i128(i128 signext %a, i128 signext %b) {
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entry:
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; ALL-LABEL: and_i128:
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; GP32: lw $[[T0:[0-9]+]], 24($sp)
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; GP32: lw $[[T1:[0-9]+]], 20($sp)
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; GP32: lw $[[T2:[0-9]+]], 16($sp)
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; GP32: and $2, $4, $[[T2]]
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; GP32: and $3, $5, $[[T1]]
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; GP32: and $4, $6, $[[T0]]
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; GP32: lw $[[T0:[0-9]+]], 20($sp)
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; GP32: lw $[[T1:[0-9]+]], 16($sp)
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; GP32: and $2, $4, $[[T1]]
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; GP32: and $3, $5, $[[T0]]
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; GP32: lw $[[T2:[0-9]+]], 24($sp)
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; GP32: and $4, $6, $[[T2]]
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; GP32: lw $[[T3:[0-9]+]], 28($sp)
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; GP32: and $5, $7, $[[T3]]
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; GP64: and $2, $4, $6
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; GP64: and $3, $5, $7
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; MM32: lw $[[T0:[0-9]+]], 32($sp)
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; MM32: lw $[[T1:[0-9]+]], 28($sp)
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; MM32: lw $[[T0:[0-9]+]], 20($sp)
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; MM32: lw $[[T1:[0-9]+]], 16($sp)
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; MM32: and16 $[[T1]], $4
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; MM32: and16 $[[T0]], $5
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; MM32: lw $[[T2:[0-9]+]], 24($sp)
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; MM32: and16 $[[T2]], $4
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; MM32: and16 $[[T1]], $5
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; MM32: and16 $[[T0]], $6
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; MM32: lw $[[T3:[0-9]+]], 36($sp)
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; MM32: and16 $[[T2]], $6
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; MM32: lw $[[T3:[0-9]+]], 28($sp)
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; MM32: and16 $[[T3]], $7
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; MM64: and $2, $4, $6
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@ -185,17 +185,17 @@ entry:
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; 32R1-R5: multu $5, $7
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; 32R1-R5: mflo $3
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; 32R1-R5: mfhi $[[T0:[0-9]+]]
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; 32R1-R5: mul $[[T1:[0-9]+]], $4, $7
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; 32R1-R5: mul $[[T2:[0-9]+]], $5, $6
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; 32R1-R5: addu $[[T0]], $[[T0]], $[[T2:[0-9]+]]
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; 32R1-R5: addu $2, $[[T0]], $[[T1]]
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; 32R1-R5: mul $[[T1:[0-9]+]], $5, $6
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; 32R1-R5: addu $[[T0]], $[[T0]], $[[T1:[0-9]+]]
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; 32R1-R5: mul $[[T2:[0-9]+]], $4, $7
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; 32R1-R5: addu $2, $[[T0]], $[[T2]]
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; 32R6-DAG: mul $[[T0:[0-9]+]], $5, $6
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; 32R6: muhu $[[T1:[0-9]+]], $5, $7
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; 32R6: addu $[[T0]], $[[T1]], $[[T0]]
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; 32R6-DAG: mul $[[T2:[0-9]+]], $4, $7
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; 32R6: addu $2, $[[T0]], $[[T2]]
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; 32R6-DAG: mul $3, $5, $7
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; 32R6-DAG: mul $[[T0:[0-9]+]], $4, $7
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; 32R6-DAG: mul $[[T1:[0-9]+]], $5, $6
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; 32R6: muhu $[[T2:[0-9]+]], $5, $7
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; 32R6: addu $[[T1]], $[[T2]], $[[T1]]
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; 32R6: addu $2, $[[T1]], $[[T0]]
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; M4: dmult $4, $5
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; M4: mflo $2
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@ -208,17 +208,17 @@ entry:
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; MM32R3: multu $[[T0:[0-9]+]], $7
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; MM32R3: mflo $[[T1:[0-9]+]]
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; MM32R3: mfhi $[[T2:[0-9]+]]
|
||||
; MM32R3: mul $[[T3:[0-9]+]], $4, $7
|
||||
; MM32R3: mul $[[T0]], $[[T0]], $6
|
||||
; MM32R3: addu16 $[[T2]], $[[T2]], $[[T0]]
|
||||
; MM32R3: addu16 $2, $[[T2]], $[[T3]]
|
||||
; MM32R3: addu16 $2, $[[T2]], $[[T0]]
|
||||
; MM32R3: mul $[[T3:[0-9]+]], $4, $7
|
||||
; MM32R3: addu16 $[[T2]], $[[T2]], $[[T3]]
|
||||
|
||||
; MM32R6: mul $[[T0:[0-9]+]], $5, $7
|
||||
; MM32R6: mul $[[T1:[0-9]+]], $4, $7
|
||||
; MM32R6: mul $[[T2:[0-9]+]], $5, $6
|
||||
; MM32R6: muhu $[[T3:[0-9]+]], $5, $7
|
||||
; MM32R6: addu16 $[[T2]], $[[T3]], $[[T2]]
|
||||
; MM32R6: addu16 $2, $[[T2]], $[[T1]]
|
||||
; MM32R6: mul $[[T0:[0-9]+]], $5, $6
|
||||
; MM32R6: muhu $[[T1:[0-9]+]], $5, $7
|
||||
; MM32R6: addu16 $[[T2:[0-9]+]], $[[T1]], $[[T0]]
|
||||
; MM32R6: mul $[[T3:[0-9]+]], $4, $7
|
||||
; MM32R6: addu16 $2, $[[T2]], $[[T3]]
|
||||
; MM32R6: mul $[[T1]], $5, $7
|
||||
|
||||
%r = mul i64 %a, %b
|
||||
ret i64 %r
|
||||
@ -240,12 +240,12 @@ entry:
|
||||
; GP64-NOT-R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
|
||||
; GP64-NOT-R6: daddu $2, $[[T3:[0-9]+]], $[[T0]]
|
||||
|
||||
; 64R6-DAG: dmul $3, $5, $7
|
||||
; 64R6-DAG: dmul $[[T0:[0-9]+]], $4, $7
|
||||
; 64R6-DAG: dmul $[[T1:[0-9]+]], $5, $6
|
||||
; 64R6: dmuhu $[[T2:[0-9]+]], $5, $7
|
||||
; 64R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
|
||||
; 64R6-DAG: dmul $[[T0:[0-9]+]], $4, $7
|
||||
; 64R6: daddu $2, $[[T1]], $[[T0]]
|
||||
; 64R6-DAG: dmul $3, $5, $7
|
||||
|
||||
; MM32: lw $25, %call16(__multi3)($16)
|
||||
|
||||
|
||||
@ -209,11 +209,11 @@ define signext i128 @nor_i128(i128 signext %a, i128 signext %b) {
|
||||
entry:
|
||||
; ALL-LABEL: nor_i128:
|
||||
|
||||
; GP32: lw $[[T0:[0-9]+]], 24($sp)
|
||||
; GP32: lw $[[T1:[0-9]+]], 20($sp)
|
||||
; GP32: lw $[[T2:[0-9]+]], 16($sp)
|
||||
; GP32: nor $2, $[[T2]], $4
|
||||
; GP32: nor $3, $[[T1]], $5
|
||||
; GP32: lw $[[T0:[0-9]+]], 24($sp)
|
||||
; GP32: nor $4, $[[T0]], $6
|
||||
; GP32: lw $[[T3:[0-9]+]], 28($sp)
|
||||
; GP32: nor $5, $[[T3]], $7
|
||||
@ -221,11 +221,11 @@ entry:
|
||||
; GP64: nor $2, $6, $4
|
||||
; GP64: nor $3, $7, $5
|
||||
|
||||
; MM32: lw $[[T0:[0-9]+]], 24($sp)
|
||||
; MM32: lw $[[T1:[0-9]+]], 20($sp)
|
||||
; MM32: lw $[[T2:[0-9]+]], 16($sp)
|
||||
; MM32: nor $2, $[[T2]], $4
|
||||
; MM32: nor $3, $[[T1]], $5
|
||||
; MM32: lw $[[T0:[0-9]+]], 24($sp)
|
||||
; MM32: nor $4, $[[T0]], $6
|
||||
; MM32: lw $[[T3:[0-9]+]], 28($sp)
|
||||
; MM32: nor $5, $[[T3]], $7
|
||||
|
||||
@ -107,11 +107,11 @@ define signext i128 @or_i128(i128 signext %a, i128 signext %b) {
|
||||
entry:
|
||||
; ALL-LABEL: or_i128:
|
||||
|
||||
; GP32: lw $[[T0:[0-9]+]], 24($sp)
|
||||
; GP32: lw $[[T1:[0-9]+]], 20($sp)
|
||||
; GP32: lw $[[T2:[0-9]+]], 16($sp)
|
||||
; GP32: or $2, $4, $[[T2]]
|
||||
; GP32: or $3, $5, $[[T1]]
|
||||
; GP32: lw $[[T0:[0-9]+]], 24($sp)
|
||||
; GP32: or $4, $6, $[[T0]]
|
||||
; GP32: lw $[[T3:[0-9]+]], 28($sp)
|
||||
; GP32: or $5, $7, $[[T3]]
|
||||
@ -119,13 +119,13 @@ entry:
|
||||
; GP64: or $2, $4, $6
|
||||
; GP64: or $3, $5, $7
|
||||
|
||||
; MM32: lw $[[T0:[0-9]+]], 32($sp)
|
||||
; MM32: lw $[[T1:[0-9]+]], 28($sp)
|
||||
; MM32: lw $[[T2:[0-9]+]], 24($sp)
|
||||
; MM32: lw $[[T1:[0-9]+]], 20($sp)
|
||||
; MM32: lw $[[T2:[0-9]+]], 16($sp)
|
||||
; MM32: or16 $[[T2]], $4
|
||||
; MM32: or16 $[[T1]], $5
|
||||
; MM32: lw $[[T0:[0-9]+]], 24($sp)
|
||||
; MM32: or16 $[[T0]], $6
|
||||
; MM32: lw $[[T3:[0-9]+]], 36($sp)
|
||||
; MM32: lw $[[T3:[0-9]+]], 28($sp)
|
||||
; MM32: or16 $[[T3]], $7
|
||||
|
||||
; MM64: or $2, $4, $6
|
||||
|
||||
@ -46,8 +46,8 @@ entry:
|
||||
; M3: mov.s $f0, $f13
|
||||
|
||||
; CMOV-32: mtc1 $6, $f0
|
||||
; CMOV-32: mtc1 $5, $f1
|
||||
; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
|
||||
; CMOV-32: mtc1 $5, $f1
|
||||
; CMOV-32: movn.s $f0, $f1, $[[T0]]
|
||||
|
||||
; SEL-32: mtc1 $5, $[[F0:f[0-9]+]]
|
||||
@ -63,8 +63,8 @@ entry:
|
||||
; SEL-64: sel.s $f0, $f14, $f13
|
||||
|
||||
; MM32R3: mtc1 $6, $[[F0:f[0-9]+]]
|
||||
; MM32R3: mtc1 $5, $[[F1:f[0-9]+]]
|
||||
; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
|
||||
; MM32R3: mtc1 $5, $[[F1:f[0-9]+]]
|
||||
; MM32R3: movn.s $f0, $[[F1]], $[[T0]]
|
||||
|
||||
%r = select i1 %s, float %x, float %y
|
||||
|
||||
@ -163,14 +163,14 @@ entry:
|
||||
; CMOV-32: movn $3, $7, $[[T0]]
|
||||
|
||||
; SEL-32: andi $[[T0:[0-9]+]], $4, 1
|
||||
; SEL-32: selnez $[[T1:[0-9]+]], $6, $[[T0]]
|
||||
; SEL-32: lw $[[T2:[0-9]+]], 16($sp)
|
||||
; SEL-32: seleqz $[[T3:[0-9]+]], $[[T2]], $[[T0]]
|
||||
; SEL-32: or $2, $[[T1]], $[[T3]]
|
||||
; SEL-32: selnez $[[T4:[0-9]+]], $7, $[[T0]]
|
||||
; SEL-32: lw $[[T5:[0-9]+]], 20($sp)
|
||||
; SEL-32: seleqz $[[T6:[0-9]+]], $[[T5]], $[[T0]]
|
||||
; SEL-32: or $3, $[[T4]], $[[T6]]
|
||||
; SEL-32: lw $[[T1:[0-9]+]], 16($sp)
|
||||
; SEL-32: seleqz $[[T2:[0-9]+]], $[[T1]], $[[T0]]
|
||||
; SEL-32: selnez $[[T3:[0-9]+]], $6, $[[T0]]
|
||||
; SEL-32: or $2, $[[T3]], $[[T2]]
|
||||
; SEL-32: lw $[[T4:[0-9]+]], 20($sp)
|
||||
; SEL-32: seleqz $[[T5:[0-9]+]], $[[T4]], $[[T0]]
|
||||
; SEL-32: selnez $[[T6:[0-9]+]], $7, $[[T0]]
|
||||
; SEL-32: or $3, $[[T6]], $[[T5]]
|
||||
|
||||
; M3: andi $[[T0:[0-9]+]], $4, 1
|
||||
; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
|
||||
@ -198,13 +198,13 @@ entry:
|
||||
; MM32R3: movn $3, $7, $[[T0]]
|
||||
|
||||
; MM32R6: andi16 $[[T0:[0-9]+]], $4, 1
|
||||
; MM32R6: selnez $[[T1:[0-9]+]], $6, $[[T0]]
|
||||
; MM32R6: lw $[[T2:[0-9]+]], 16($sp)
|
||||
; MM32R6: seleqz $[[T3:[0-9]+]], $[[T2]], $[[T0]]
|
||||
; MM32R6: selnez $[[T1:[0-9]+]], $6, $[[T0]]
|
||||
; MM32R6: or $2, $[[T1]], $[[T3]]
|
||||
; MM32R6: selnez $[[T6:[0-9]+]], $7, $[[T0]]
|
||||
; MM32R6: lw $[[T4:[0-9]+]], 20($sp)
|
||||
; MM32R6: seleqz $[[T5:[0-9]+]], $[[T4]], $[[T0]]
|
||||
; MM32R6: selnez $[[T6:[0-9]+]], $7, $[[T0]]
|
||||
; MM32R6: or $3, $[[T6]], $[[T5]]
|
||||
|
||||
%r = select i1 %s, i64 %x, i64 %y
|
||||
|
||||
@ -134,16 +134,16 @@ entry:
|
||||
; GP32-MM: sltu $[[T1:[0-9]+]], $[[T2:[0-9]+]], $[[T0]]
|
||||
; GP32-MM: lw $[[T3:[0-9]+]], 16($sp)
|
||||
; GP32-MM: addu $[[T3]], $[[T1]], $[[T3]]
|
||||
; GP32-MM: lw $[[T5:[0-9]+]], 24($sp)
|
||||
; GP32-MM: lw $[[T4:[0-9]+]], 28($sp)
|
||||
; GP32-MM: subu $[[T1]], $7, $[[T4]]
|
||||
; GP32-MM: subu $[[T3]], $4, $[[T3]]
|
||||
; GP32-MM: sltu $[[T6:[0-9]+]], $6, $[[T5]]
|
||||
; GP32-MM: lw $[[T4:[0-9]+]], 24($sp)
|
||||
; GP32-MM: lw $[[T5:[0-9]+]], 28($sp)
|
||||
; GP32-MM: subu $[[T1]], $7, $[[T5]]
|
||||
; GP32-MM: subu $[[T3]], $[[T6:[0-9]+]], $[[T3]]
|
||||
; GP32-MM: sltu $[[T6]], $6, $[[T4]]
|
||||
; GP32-MM: addu $[[T0]], $[[T6]], $[[T0]]
|
||||
; GP32-MM: subu $[[T0]], $5, $[[T0]]
|
||||
; GP32-MM: sltu $[[T7:[0-9]+]], $7, $[[T4]]
|
||||
; GP32-MM: addu $[[T8:[0-8]+]], $[[T7]], $[[T5]]
|
||||
; GP32-MM: subu $[[T9:[0-9]+]], $6, $[[T8]]
|
||||
; GP32-MM: sltu $[[T6]], $7, $[[T5]]
|
||||
; GP32-MM: addu $[[T6]], $[[T6]], $[[T4]]
|
||||
; GP32-MM: subu $[[T6]], $6, $[[T6]]
|
||||
; GP32-MM: move $[[T2]], $[[T1]]
|
||||
|
||||
; GP64: dsubu $3, $5, $7
|
||||
|
||||
@ -117,11 +117,11 @@ define signext i128 @xor_i128(i128 signext %a, i128 signext %b) {
|
||||
entry:
|
||||
; ALL-LABEL: xor_i128:
|
||||
|
||||
; GP32: lw $[[T0:[0-9]+]], 24($sp)
|
||||
; GP32: lw $[[T1:[0-9]+]], 20($sp)
|
||||
; GP32: lw $[[T2:[0-9]+]], 16($sp)
|
||||
; GP32: xor $2, $4, $[[T2]]
|
||||
; GP32: xor $3, $5, $[[T1]]
|
||||
; GP32: lw $[[T0:[0-9]+]], 24($sp)
|
||||
; GP32: xor $4, $6, $[[T0]]
|
||||
; GP32: lw $[[T3:[0-9]+]], 28($sp)
|
||||
; GP32: xor $5, $7, $[[T3]]
|
||||
@ -129,13 +129,13 @@ entry:
|
||||
; GP64: xor $2, $4, $6
|
||||
; GP64: xor $3, $5, $7
|
||||
|
||||
; MM32: lw $[[T0:[0-9]+]], 32($sp)
|
||||
; MM32: lw $[[T1:[0-9]+]], 28($sp)
|
||||
; MM32: lw $[[T2:[0-9]+]], 24($sp)
|
||||
; MM32: lw $[[T1:[0-9]+]], 20($sp)
|
||||
; MM32: lw $[[T2:[0-9]+]], 16($sp)
|
||||
; MM32: xor16 $[[T2]], $4
|
||||
; MM32: xor16 $[[T1]], $5
|
||||
; MM32: lw $[[T0:[0-9]+]], 24($sp)
|
||||
; MM32: xor16 $[[T0]], $6
|
||||
; MM32: lw $[[T3:[0-9]+]], 36($sp)
|
||||
; MM32: lw $[[T3:[0-9]+]], 28($sp)
|
||||
; MM32: xor16 $[[T3]], $7
|
||||
|
||||
; MM64: xor $2, $4, $6
|
||||
|
||||
@ -102,8 +102,8 @@ end:
|
||||
|
||||
; N64: [[BB0]]:
|
||||
; N64: daddiu $[[GP:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test1)))
|
||||
; N64: ld $[[R2:[0-9]+]], %got_disp(x)($[[GP]])
|
||||
; N64: addiu $[[R3:[0-9]+]], $zero, 1
|
||||
; N64: ld $[[R2:[0-9]+]], %got_disp(x)($[[GP]])
|
||||
; N64: sw $[[R3]], 0($[[R2]])
|
||||
; N64: [[BB2]]:
|
||||
; N64: jr $ra
|
||||
|
||||
@ -19,6 +19,9 @@ entry:
|
||||
;
|
||||
; On the other hand, if odd single precision registers are not permitted, it
|
||||
; will be forced to spill/reload either %a or %0.
|
||||
;
|
||||
; This is affected by scheduling as the new machine scheduler schedules the
|
||||
; two adds together, avoiding the spill+reload.
|
||||
|
||||
%0 = fadd float %a, 1.0
|
||||
call void asm "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
|
||||
@ -27,15 +30,15 @@ entry:
|
||||
}
|
||||
|
||||
; ALL-LABEL: two_floats:
|
||||
; ODDSPREG: add.s $f13, $f12, ${{f[0-9]+}}
|
||||
; ODDSPREG: add.s $f[[RES:[0-9]]], $f12, ${{f[0-9]+}}
|
||||
; ODDSPREG: add.s ${{f[0-9]+}}, $f12, $f[[RES]]
|
||||
; ODDSPREG-NOT: swc1
|
||||
; ODDSPREG-NOT: lwc1
|
||||
; ODDSPREG: add.s $f0, $f12, $f13
|
||||
|
||||
; NOODDSPREG: add.s $[[T0:f[0-9]*[02468]]], $f12, ${{f[0-9]+}}
|
||||
; NOODDSPREG: swc1 $[[T0]],
|
||||
; NOODDSPREG: lwc1 $[[T1:f[0-9]*[02468]]],
|
||||
; NOODDSPREG: add.s $f0, $f12, $[[T1]]
|
||||
; NOODDSPREG-NOT: swc1 $[[T0]],
|
||||
; NOODDSPREG-NOT: lwc1 $[[T1:f[0-9]*[02468]]],
|
||||
; NOODDSPREG: add.s ${{f[0-9]+}}, $f12, $[[T0]]
|
||||
|
||||
define double @two_doubles(double %a) {
|
||||
entry:
|
||||
@ -51,8 +54,8 @@ entry:
|
||||
}
|
||||
|
||||
; ALL-LABEL: two_doubles:
|
||||
; ALL: add.d $[[T0:f[0-9]+]], $f12, ${{f[0-9]+}}
|
||||
; ALL: add.d $f0, $f12, $[[T0]]
|
||||
; ALL-DAG: add.d $[[T0:f[0-9]+]], $f12, ${{f[0-9]+}}
|
||||
; ALL-DAG: add.d $f0, $f12, $[[T0]]
|
||||
|
||||
|
||||
; INVALID: -mattr=+nooddspreg is not currently permitted for a 32-bit FPU register file (FR=0 mode).
|
||||
|
||||
@ -13,17 +13,17 @@
|
||||
; The check for first "addiu" instruction is added so that we can match the correct "b" instruction.
|
||||
; CHECK: andi
|
||||
; CHECK: b $[[BB0:BB[0-9_]+]]
|
||||
; CHECK-NEXT: sll
|
||||
; CHECK: sll
|
||||
|
||||
; Check that at the start of a fallthrough block there is a instruction that writes to $1.
|
||||
; CHECK-NEXT: {{BB[0-9_#]+}}:
|
||||
; CHECK-NEXT: lw $[[R1:[0-9]+]], %got(assignSE2partition)($[[R2:[0-9]+]])
|
||||
; CHECK-NEXT: sll $1, $[[R0:[0-9]+]], 4
|
||||
; CHECK: {{BB[0-9_#]+}}:
|
||||
; CHECK: sll $1, $[[R0:[0-9]+]], 4
|
||||
; CHECK: lw $[[R1:[0-9]+]], %got(assignSE2partition)($[[R2:[0-9]+]])
|
||||
|
||||
; Check that identical instructions are at the start of a target block.
|
||||
; CHECK: [[BB0]]:
|
||||
; CHECK-NEXT: lw $[[R1]], %got(assignSE2partition)($[[R2]])
|
||||
; CHECK-NEXT: sll $1, $[[R0]], 4
|
||||
; CHECK: sll $1, $[[R0]], 4
|
||||
; CHECK: lw $[[R1]], %got(assignSE2partition)($[[R2]])
|
||||
|
||||
|
||||
%struct.img_par = type { i32, i32, i32, i32, i32*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [16 x [16 x i16]], [6 x [32 x i32]], [16 x [16 x i32]], [4 x [12 x [4 x [4 x i32]]]], [16 x i32], i8**, i32*, i32***, i32**, i32, i32, i32, i32, %struct.Slice*, %struct.macroblock*, i32, i32, i32, i32, i32, i32, %struct.DecRefPicMarking_s*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32***, i32***, i32****, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x [2 x i32]], [3 x [2 x i32]], i32, i32, i32, i32, %struct.timeb, %struct.timeb, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
|
||||
|
||||
@ -29,7 +29,7 @@ declare void @foo(i32*)
|
||||
;
|
||||
; x -> DW_OP_reg1(51)
|
||||
; F0: [[LOC]]: Beginning address offset: 0x0000000000000028
|
||||
; F0: Ending address offset: 0x0000000000000030
|
||||
; F0: Ending address offset: 0x000000000000002c
|
||||
; F0: Location description: 51
|
||||
|
||||
define i32 @f0(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d, i32 signext %e) !dbg !4 {
|
||||
@ -65,7 +65,7 @@ entry:
|
||||
|
||||
; x -> DW_OP_reg1(51)
|
||||
; F1: [[LOC]]: Beginning address offset: 0x0000000000000080
|
||||
; F1: Ending address offset: 0x0000000000000088
|
||||
; F1: Ending address offset: 0x0000000000000084
|
||||
; F1: Location description: 51
|
||||
|
||||
define i32 @f1(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d, i32 signext %e) !dbg !15 {
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user