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Mask directive completed with CalleeSave info
Comments for Mips directives added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41526 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
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2d4575ea5a
commit
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@ -31,6 +31,7 @@
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Mangler.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/CommandLine.h"
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@ -62,12 +63,14 @@ namespace {
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void printMemOperand(const MachineInstr *MI, int opNum,
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const char *Modifier = 0);
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unsigned int getSavedRegsBitmask(bool isFloat, MachineFunction &MF);
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void printHex32(unsigned int Value);
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void emitFunctionStart(MachineFunction &MF);
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void emitFunctionEnd();
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void emitFrameDirective(MachineFunction &MF);
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void emitMaskDirective(MachineFunction &MF);
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void emitFMaskDirective();
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void emitFMaskDirective(MachineFunction &MF);
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void emitSetDirective(SetDirectiveFlags Flag);
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bool printInstruction(const MachineInstr *MI); // autogenerated.
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@ -89,12 +92,72 @@ FunctionPass *llvm::createMipsCodePrinterPass(std::ostream &o,
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return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo());
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}
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/// This pattern will be emitted :
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/// .frame reg1, size, reg2
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/// It describes the stack frame.
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/// reg1 - stack pointer
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/// size - stack size allocated for the function
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/// reg2 - return address register
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//===----------------------------------------------------------------------===//
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//
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// Mips Asm Directives
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//
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// -- Frame directive "frame Stackpointer, Stacksize, RARegister"
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// Describe the stack frame.
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//
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// -- Mask directives "(f)mask bitmask, offset"
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// Tells the assembler which registers are saved and where.
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// bitmask - contain a little endian bitset indicating which registers are
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// saved on function prologue (e.g. with a 0x80000000 mask, the
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// assembler knows the register 31 (RA) is saved at prologue.
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// offset - the position before stack pointer subtraction indicating where
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// the first saved register on prologue is located. (e.g. with a
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//
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// Consider the following function prologue:
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//
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// .frame $fp,48,$ra
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// .mask 0xc0000000,-8
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// addiu $sp, $sp, -48
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// sw $ra, 40($sp)
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// sw $fp, 36($sp)
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//
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// With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
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// 30 (FP) are saved at prologue. As the save order on prologue is from
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// left to right, RA is saved first. A -8 offset means that after the
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// stack pointer subtration, the first register in the mask (RA) will be
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// saved at address 48-8=40.
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//
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//===----------------------------------------------------------------------===//
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/// Mask directive for GPR
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void MipsAsmPrinter::
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emitMaskDirective(MachineFunction &MF)
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{
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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int StackSize = MF.getFrameInfo()->getStackSize();
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int Offset = (!MipsFI->getTopSavedRegOffset()) ? 0 :
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(-(StackSize-MipsFI->getTopSavedRegOffset()));
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#ifndef NDEBUG
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DOUT << "--> emitMaskDirective" << "\n";
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DOUT << "StackSize : " << StackSize << "\n";
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DOUT << "getTopSavedReg : " << MipsFI->getTopSavedRegOffset() << "\n";
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DOUT << "Offset : " << Offset << "\n\n";
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#endif
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unsigned int Bitmask = getSavedRegsBitmask(false, MF);
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O << "\t.mask\t";
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printHex32(Bitmask);
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O << "," << Offset << "\n";
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}
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/// TODO: Mask Directive for Float Point
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void MipsAsmPrinter::
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emitFMaskDirective(MachineFunction &MF)
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{
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unsigned int Bitmask = getSavedRegsBitmask(true, MF);
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O << "\t.fmask\t";
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printHex32(Bitmask);
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O << ",0" << "\n";
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}
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/// Frame Directive
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void MipsAsmPrinter::
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emitFrameDirective(MachineFunction &MF)
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{
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@ -111,74 +174,10 @@ emitFrameDirective(MachineFunction &MF)
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<< "\n";
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}
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/// This pattern will be emitted :
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/// .mask bitmask, offset
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/// Tells the assembler (and possibly linker) which registers are saved and where.
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/// bitmask - mask of all GPRs (little endian)
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/// offset - negative value. offset+stackSize should give where on the stack
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/// the first GPR is saved.
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/// TODO: consider calle saved GPR regs here, not hardcode register numbers.
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void MipsAsmPrinter::
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emitMaskDirective(MachineFunction &MF)
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{
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const MRegisterInfo &RI = *TM.getRegisterInfo();
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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bool hasFP = RI.hasFP(MF);
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bool saveRA = MF.getFrameInfo()->hasCalls();
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int offset;
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if (!MipsFI->getTopSavedRegOffset())
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offset = 0;
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else
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offset = -(MF.getFrameInfo()->getStackSize()
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-MipsFI->getTopSavedRegOffset());
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#ifndef NDEBUG
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DOUT << "<--ASM PRINTER--emitMaskDirective-->" << "\n";
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DOUT << "StackSize : " << MF.getFrameInfo()->getStackSize() << "\n";
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DOUT << "getTopSavedRegOffset() : " << MipsFI->getTopSavedRegOffset() << "\n";
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DOUT << "offset : " << offset << "\n\n";
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#endif
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unsigned int bitmask = 0;
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if (hasFP)
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bitmask |= (1 << 30);
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if (saveRA)
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bitmask |= (1 << 31);
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O << "\t.mask\t";
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printHex32(bitmask);
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O << "," << offset << "\n";
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}
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/// This pattern will be emitted :
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/// .fmask bitmask, offset
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/// Tells the assembler (and possibly linker) which float registers are saved.
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/// bitmask - mask of all Float Point registers (little endian)
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/// offset - negative value. offset+stackSize should give where on the stack
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/// the first Float Point register is saved.
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/// TODO: implement this, dummy for now
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void MipsAsmPrinter::
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emitFMaskDirective()
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{
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O << "\t.fmask\t0x00000000,0" << "\n";
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}
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/// Print a 32 bit hex number filling with 0's on the left.
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/// TODO: make this setfill and setw
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void MipsAsmPrinter::
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printHex32(unsigned int Value) {
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O << "0x" << std::hex << Value << std::dec;
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}
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/// Emit Set directives.
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void MipsAsmPrinter::
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emitSetDirective(SetDirectiveFlags Flag) {
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emitSetDirective(SetDirectiveFlags Flag)
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{
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O << "\t.set\t";
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switch(Flag) {
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case REORDER: O << "reorder" << "\n"; break;
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@ -187,6 +186,45 @@ emitSetDirective(SetDirectiveFlags Flag) {
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case NOMACRO: O << "nomacro" << "\n"; break;
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default: break;
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}
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}
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// Create a bitmask with all callee saved registers for CPU
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// or Float Point registers. For CPU registers consider RA,
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// GP and FP for saving if necessary.
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unsigned int MipsAsmPrinter::
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getSavedRegsBitmask(bool isFloat, MachineFunction &MF)
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{
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const MRegisterInfo &RI = *TM.getRegisterInfo();
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// Float Point Registers, TODO
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if (isFloat)
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return 0;
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// CPU Registers
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unsigned int Bitmask = 0;
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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for (unsigned i = 0, e = CSI.size(); i != e; ++i)
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Bitmask |= (1 << MipsRegisterInfo::getRegisterNumbering(CSI[i].getReg()));
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if (RI.hasFP(MF))
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Bitmask |= (1 << MipsRegisterInfo::getRegisterNumbering(RI.getFrameRegister(MF)));
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if (MF.getFrameInfo()->hasCalls())
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Bitmask |= (1 << MipsRegisterInfo::getRegisterNumbering(RI.getRARegister()));
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return Bitmask;
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}
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// Print a 32 bit hex number with all numbers.
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void MipsAsmPrinter::
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printHex32(unsigned int Value)
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{
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O << "0x" << std::hex;
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for (int i = 7; i >= 0; i--)
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O << std::hex << ( (Value & (0xF << (i*4))) >> (i*4) );
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O << std::dec;
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}
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/// Emit the directives used by GAS on the start of functions
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@ -208,7 +246,7 @@ emitFunctionStart(MachineFunction &MF)
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emitFrameDirective(MF);
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emitMaskDirective(MF);
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emitFMaskDirective();
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emitFMaskDirective(MF);
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emitSetDirective(NOREORDER);
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emitSetDirective(NOMACRO);
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O << "\n";
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@ -420,6 +458,7 @@ doFinalization(Module &M)
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default:
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assert(0 && "Unknown linkage type!");
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}
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O << "\t.align " << Align << "\n";
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O << "\t.type " << name << ",@object\n";
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O << "\t.size " << name << "," << Size << "\n";
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@ -22,8 +22,7 @@ namespace llvm {
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namespace Mips {
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// All CC branch operations on Mips I are turned
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// into BEQ and BNE CC branches instructions.
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// Mips Condition Codes
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enum CondCode {
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COND_E,
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COND_GZ,
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