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GlobalISel: verify that generic loads & stores have a mem operand.

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The mem operand is used by GlobalISel to convey atomic constraints so dropping
it is invalid.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295476 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2017-02-17 18:50:15 +00:00
parent 9053922e7e
commit dc88467192
5 changed files with 28 additions and 20 deletions
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8
lib/CodeGen/MachineVerifier.cpp
View File

@ -908,6 +908,14 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
}
}
// Generic loads and stores must have a single MachineMemOperand
// describing that access.
if ((MI->getOpcode() == TargetOpcode::G_LOAD ||
MI->getOpcode() == TargetOpcode::G_STORE) &&
!MI->hasOneMemOperand())
report("Generic instruction accessing memory must have one mem operand",
MI);
StringRef ErrorInfo;
if (!TII->verifyInstruction(*MI, ErrorInfo))
report(ErrorInfo.data(), MI);

4
test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
View File

@ -622,7 +622,7 @@ body: |
; CHECK: %0(p0) = COPY %x0
; CHECK: %1(s32) = G_LOAD %0
%0(p0) = COPY %x0
%1(s32) = G_LOAD %0
%1(s32) = G_LOAD %0 :: (load 4)
...
---
@ -643,7 +643,7 @@ body: |
; CHECK: G_STORE %1(s32), %0(p0)
%0(p0) = COPY %x0
%1(s32) = COPY %w1
G_STORE %1, %0
G_STORE %1, %0 :: (store 4)
...
---

8
test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
View File

@ -320,13 +320,13 @@ body: |
%0(p0) = G_FRAME_INDEX %fixed-stack.2
; CHECK: [[FI32VREG:%[0-9]+]] = ADDri %fixed-stack.[[FI32]], 0, 14, _, _
%1(s32) = G_LOAD %0(p0)
%1(s32) = G_LOAD %0(p0) :: (load 4)
; CHECK: {{%[0-9]+}} = LDRi12 [[FI32VREG]], 0, 14, _
%2(p0) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[FI1VREG:%[0-9]+]] = ADDri %fixed-stack.[[FI1]], 0, 14, _, _
%3(s1) = G_LOAD %2(p0)
%3(s1) = G_LOAD %2(p0) :: (load 1)
; CHECK: {{%[0-9]+}} = LDRBi12 [[FI1VREG]], 0, 14, _
BX_RET 14, _
@ -350,7 +350,7 @@ body: |
%0(p0) = COPY %r0
%1(s32) = G_LOAD %0(p0)
%1(s32) = G_LOAD %0(p0) :: (load 4)
; CHECK: %[[V]] = VLDRS %[[P]], 0, 14, _
%s0 = COPY %1
@ -377,7 +377,7 @@ body: |
%0(p0) = COPY %r0
%1(s64) = G_LOAD %0(p0)
%1(s64) = G_LOAD %0(p0) :: (load 8)
; CHECK: %[[V]] = VLDRD %[[P]], 0, 14, _
%d0 = COPY %1

16
test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
View File

@ -157,9 +157,9 @@ body: |
; This is legal, so we should find it unchanged in the output
; CHECK: [[FIVREG:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[FRAME_INDEX]]
; CHECK: {{%[0-9]+}}(s32) = G_LOAD [[FIVREG]](p0)
; CHECK: {{%[0-9]+}}(s32) = G_LOAD [[FIVREG]](p0) :: (load 4)
%0(p0) = G_FRAME_INDEX %fixed-stack.2
%1(s32) = G_LOAD %0(p0)
%1(s32) = G_LOAD %0(p0) :: (load 4)
BX_RET 14, _
...
---
@ -190,12 +190,12 @@ body: |
; CHECK-DAG: {{%[0-9]+}}(s1) = G_LOAD %0
; CHECK-DAG: {{%[0-9]+}}(p0) = G_LOAD %0
%0(p0) = COPY %r0
%1(s32) = G_LOAD %0(p0)
%2(s16) = G_LOAD %0(p0)
%3(s8) = G_LOAD %0(p0)
%4(s1) = G_LOAD %0(p0)
%5(p0) = G_LOAD %0(p0)
%6(s64) = G_LOAD %0(p0)
%1(s32) = G_LOAD %0(p0) :: (load 4)
%2(s16) = G_LOAD %0(p0) :: (load 2)
%3(s8) = G_LOAD %0(p0) :: (load 1)
%4(s1) = G_LOAD %0(p0) :: (load 1)
%5(p0) = G_LOAD %0(p0) :: (load 4)
%6(s64) = G_LOAD %0(p0) :: (load 8)
BX_RET 14, _
...
---

12
test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
View File

@ -145,12 +145,12 @@ body: |
bb.0:
liveins: %r0
%0(p0) = COPY %r0
%6(s64) = G_LOAD %0
%1(s32) = G_LOAD %0
%2(s16) = G_LOAD %0
%3(s8) = G_LOAD %0
%4(s1) = G_LOAD %0
%5(p0) = G_LOAD %0
%6(s64) = G_LOAD %0 :: (load 8)
%1(s32) = G_LOAD %0 :: (load 4)
%2(s16) = G_LOAD %0 :: (load 2)
%3(s8) = G_LOAD %0 :: (load 1)
%4(s1) = G_LOAD %0 :: (load 1)
%5(p0) = G_LOAD %0 :: (load 8)
BX_RET 14, _, implicit %r0
...