From dcfa0f7a408e54f15f0237daf2336df852053c6b Mon Sep 17 00:00:00 2001 From: Joey Gouly Date: Tue, 27 Aug 2013 11:24:16 +0000 Subject: [PATCH] [ARMv8] Add some negative tests for the recent VFP/NEON instructions. Fix two issues I found while writing these tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189341 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrNEON.td | 4 +- lib/Target/ARM/ARMInstrVFP.td | 5 ++ test/MC/ARM/invalid-neon-v8.s | 26 +++++++++++ test/MC/ARM/invalid-v8fp.s | 85 ++++++++++++++++++++++++++++++++-- 4 files changed, 115 insertions(+), 5 deletions(-) create mode 100644 test/MC/ARM/invalid-neon-v8.s diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index e86e658d9d8..a5d898540ba 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -5758,9 +5758,9 @@ multiclass VRINT_FPI op9_7, SDPatternOperator Int> { } } - def : InstAlias(NAME#"D") DPR:$Dd, DPR:$Dm)>; - def : InstAlias(NAME#"Q") QPR:$Qd, QPR:$Qm)>; } diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td index 3bb4d6f97f9..34d83c6446d 100644 --- a/lib/Target/ARM/ARMInstrVFP.td +++ b/lib/Target/ARM/ARMInstrVFP.td @@ -669,6 +669,11 @@ multiclass vrint_inst_zrx { let Inst{7} = op2; let Inst{16} = op; } + + def : InstAlias(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p)>; + def : InstAlias(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p)>; } defm VRINTZ : vrint_inst_zrx<"z", 0, 1>; diff --git a/test/MC/ARM/invalid-neon-v8.s b/test/MC/ARM/invalid-neon-v8.s new file mode 100644 index 00000000000..bdcb6fbe779 --- /dev/null +++ b/test/MC/ARM/invalid-neon-v8.s @@ -0,0 +1,26 @@ +@ RUN: not llvm-mc -triple armv8 -mattr=+neon -show-encoding < %s 2>&1 | FileCheck %s + +vmaxnm.f32 s4, d5, q1 +@ CHECK: error: invalid operand for instruction +vmaxnm.f64.f64 s4, d5, q1 +@ CHECK: error: invalid operand for instruction +vmaxnmge.f64.f64 s4, d5, q1 +@ CHECK: error: instruction 'vmaxnm' is not predicable, but condition code specified + +vcvta.s32.f32 s1, s2 +@ CHECK: error: instruction requires: V8FP +vcvtp.u32.f32 s1, d2 +@ CHECK: error: invalid operand for instruction +vcvtp.f32.u32 d1, q2 +@ CHECK: error: invalid operand for instruction +vcvtplo.f32.u32 s1, s2 +@ CHECK: error: instruction 'vcvtp' is not predicable, but condition code specified + +vrinta.f64.f64 s3, d12 +@ CHECK: error: invalid operand for instruction +vrintn.f32 d3, q12 +@ CHECK: error: invalid operand for instruction +vrintz.f32 d3, q12 +@ CHECK: error: invalid operand for instruction +vrintmge.f32.f32 d3, d4 +@ CHECK: error: instruction 'vrintm' is not predicable, but condition code specified diff --git a/test/MC/ARM/invalid-v8fp.s b/test/MC/ARM/invalid-v8fp.s index 4dff188b8e5..b5d572e5b5f 100644 --- a/test/MC/ARM/invalid-v8fp.s +++ b/test/MC/ARM/invalid-v8fp.s @@ -1,10 +1,89 @@ -@ RUN: not llvm-mc -triple armv7 -show-encoding < %s | FileCheck %s +@ RUN: not llvm-mc -triple armv8 -show-encoding -mattr=+v8fp < %s 2>&1 | FileCheck %s --check-prefix=V8 @ VCVT{B,T} vcvtt.f64.f16 d3, s1 -@ CHECK-NOT: vcvtt.f64.f16 d3, s1 @ encoding: [0xe0,0x3b,0xb2,0xee] +@ V7-NOT: vcvtt.f64.f16 d3, s1 @ encoding: [0xe0,0x3b,0xb2,0xee] vcvtt.f16.f64 s5, d12 -@ CHECK-NOT: vcvtt.f16.f64 s5, d12 @ encoding: [0xcc,0x2b,0xf3,0xee] +@ V7-NOT: vcvtt.f16.f64 s5, d12 @ encoding: [0xcc,0x2b,0xf3,0xee] + vsel.f32 s3, s4, s6 +@ V8: error: invalid instruction + vselne.f32 s3, s4, s6 +@ V8: error: invalid instruction + vselmi.f32 s3, s4, s6 +@ V8: error: invalid instruction + vselpl.f32 s3, s4, s6 +@ V8: error: invalid instruction + vselvc.f32 s3, s4, s6 +@ V8: error: invalid instruction + vselcs.f32 s3, s4, s6 +@ V8: error: invalid instruction + vselcc.f32 s3, s4, s6 +@ V8: error: invalid instruction + vselhs.f32 s3, s4, s6 +@ V8: error: invalid instruction + vsello.f32 s3, s4, s6 +@ V8: error: invalid instruction + vselhi.f32 s3, s4, s6 +@ V8: error: invalid instruction + vsells.f32 s3, s4, s6 +@ V8: error: invalid instruction + vsellt.f32 s3, s4, s6 +@ V8: error: invalid instruction + vselle.f32 s3, s4, s6 +@ V8: error: invalid instruction +vseleq.f32 s0, d2, d1 +@ V8: error: invalid operand for instruction +vselgt.f64 s3, s2, s1 +@ V8: error: invalid operand for instruction +vselgt.f32 s0, q3, q1 +@ V8: error: invalid operand for instruction +vselgt.f64 q0, s3, q1 +@ V8: error: invalid operand for instruction + +vmaxnm.f32 s0, d2, d1 +@ V8: error: invalid operand for instruction +vminnm.f64 s3, s2, s1 +@ V8: error: invalid operand for instruction +vmaxnm.f32 s0, q3, q1 +@ V8: error: invalid operand for instruction +vmaxnm.f64 q0, s3, q1 +@ V8: error: invalid operand for instruction +vmaxnmgt.f64 q0, s3, q1 +@ CHECK: error: instruction 'vmaxnm' is not predicable, but condition code specified + +vcvta.s32.f64 d3, s2 +@ V8: error: invalid operand for instruction +vcvtp.s32.f32 d3, s2 +@ V8: error: invalid operand for instruction +vcvtn.u32.f64 d3, s2 +@ V8: error: invalid operand for instruction +vcvtm.u32.f32 d3, s2 +@ V8: error: invalid operand for instruction +vcvtnge.u32.f64 d3, s2 +@ V8: error: instruction 'vcvtn' is not predicable, but condition code specified + +vcvtbgt.f64.f16 q0, d3 +@ V8: error: invalid operand for instruction +vcvttlt.f64.f16 s0, s3 +@ V8: error: invalid operand for instruction +vcvttvs.f16.f64 s0, s3 +@ V8: error: invalid operand for instruction +vcvtthi.f16.f64 q0, d3 +@ V8: error: invalid operand for instruction + +vrintrlo.f32.f32 d3, q0 +@ V8: error: invalid operand for instruction +vrintxcs.f32.f32 d3, d0 +@ V8: error: instruction requires: NEON + +vrinta.f64.f64 s3, q0 +@ V8: error: invalid operand for instruction +vrintn.f32.f32 d3, d0 +@ V8: error: instruction requires: NEON +vrintp.f32 q3, q0 +@ V8: error: instruction requires: NEON +vrintmlt.f32 q3, q0 +@ V8: error: instruction 'vrintm' is not predicable, but condition code specified