RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-11-29 22:50:47 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Fix PR14314

Browse Source 
- Fix operand order for atomic sub, where the minuend is the value
  loaded from memory and the subtrahend is the parameter specified.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167718 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Michael Liao 2012-11-12 06:49:17 +00:00
parent 8ee3963409
commit dd3383fd09
3 changed files with 19 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/X86/X86ISelLowering.cpp
View File

@ -12729,8 +12729,8 @@ X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
case X86::ATOMSUB6432: {
unsigned HiOpc;
unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
BuildMI(mainMBB, DL, TII->get(LoOpc), t1L).addReg(SrcLoReg).addReg(LoReg);
BuildMI(mainMBB, DL, TII->get(HiOpc), t1H).addReg(SrcHiReg).addReg(HiReg);
BuildMI(mainMBB, DL, TII->get(LoOpc), t1L).addReg(LoReg).addReg(SrcLoReg);
BuildMI(mainMBB, DL, TII->get(HiOpc), t1H).addReg(HiReg).addReg(SrcHiReg);
break;
}
case X86::ATOMNAND6432: {

8
test/CodeGen/X86/2010-01-08-Atomic64Bug.ll
View File

@ -10,10 +10,10 @@ entry:
; CHECK: movl ([[REG:%[a-z]+]]), %eax
; CHECK: movl 4([[REG]]), %edx
; CHECK: LBB0_1:
; CHECK: movl $1
; CHECK: addl
; CHECK: movl $0
; CHECK: adcl
; CHECK: movl %eax, %ebx
; CHECK: addl {{%[a-z]+}}, %ebx
; CHECK: movl %edx, %ecx
; CHECK: adcl {{%[a-z]+}}, %ecx
; CHECK: lock
; CHECK-NEXT: cmpxchg8b ([[REG]])
; CHECK-NEXT: jne

13
test/CodeGen/X86/pr14314.ll Normal file
View File

@ -0,0 +1,13 @@
; RUN: llc < %s -mtriple=i386-pc-linux -mcpu=corei7 | FileCheck %s
define i64 @atomicSub(i64* %a, i64 %b) nounwind {
entry:
%0 = atomicrmw sub i64* %a, i64 %b seq_cst
ret i64 %0
; CHECK: atomicSub
; movl %eax, %ebx
; subl {{%[a-z]+}}, %ebx
; movl %edx, %ecx
; sbbl {{%[a-z]+}}, %ecx
; CHECK: ret
}