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[mips] Implement tlbp, tlbr, tlbwi, and tlbwr

Browse Source 
Reviewers: vmedic, dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3571

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208301 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2014-05-08 11:51:18 +00:00
parent a054f10ffe
commit dd9080a246
20 changed files with 52 additions and 36 deletions
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9
lib/Target/Mips/MipsInstrFormats.td
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@ -843,3 +843,12 @@ class BARRIER_FM<bits<5> op> : StdArch {
let Inst{10-6} = op; // Operation
let Inst{5-0} = 0; // SLL
}
class COP0_TLB_FM<bits<6> op> : StdArch {
bits<32> Inst;
let Inst{31-26} = 0x10; // COP0
let Inst{25} = 1; // CO
let Inst{24-6} = 0;
let Inst{5-0} = op; // Operation
}

7
lib/Target/Mips/MipsInstrInfo.td
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@ -1207,6 +1207,13 @@ def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
def EHB : Barrier<"ehb">, BARRIER_FM<3>;
def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
FrmOther>;
def TLBP : TLB<"tlbp">, COP0_TLB_FM<0x08>;
def TLBR : TLB<"tlbr">, COP0_TLB_FM<0x01>;
def TLBWI : TLB<"tlbwi">, COP0_TLB_FM<0x02>;
def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>;
//===----------------------------------------------------------------------===//
// Instruction aliases
//===----------------------------------------------------------------------===//

4
test/MC/Mips/mips1/valid-xfail.s
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@ -7,10 +7,6 @@
# XFAIL: *
.set noat
tlbp
tlbr
tlbwi
tlbwr
lwc0 c0_entrylo,-7321($s2)
lwc3 $10,-32265($k0)
swc0 c0_prid,18904($s3)

4
test/MC/Mips/mips1/valid.s
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@ -92,4 +92,8 @@
swc2 $25,24880($s0)
swl $t7,13694($s3)
swr $s1,-26590($t6)
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
xor $s2,$a0,$s8

4
test/MC/Mips/mips2/valid-xfail.s
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@ -10,7 +10,3 @@
ldc3 $29,-28645($s1)
lwc3 $10,-32265($k0)
sdc3 $12,5835($t2)
tlbp
tlbr
tlbwi
tlbwr

4
test/MC/Mips/mips2/valid.s
View File

@ -109,6 +109,10 @@
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
tlti $t6,-21059
tltiu $ra,-5076
tnei $t4,-29647

4
test/MC/Mips/mips3/valid-xfail.s
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@ -8,7 +8,3 @@
.set noat
lwc3 $10,-32265($k0)
tlbp
tlbr
tlbwi
tlbwr

4
test/MC/Mips/mips3/valid.s
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@ -159,6 +159,10 @@
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
tlti $t6,-21059
tltiu $ra,-5076
tnei $t4,-29647

4
test/MC/Mips/mips32/valid-xfail.s
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@ -38,7 +38,3 @@
ldc3 $29,-28645($s1)
rorv $t5,$a3,$s5
sdc3 $12,5835($t2)
tlbp
tlbr
tlbwi
tlbwr

4
test/MC/Mips/mips32/valid.s
View File

@ -134,6 +134,10 @@
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
tlti $t6,-21059
tltiu $ra,-5076
tnei $t4,-29647

4
test/MC/Mips/mips32r2/valid-xfail.s
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@ -304,10 +304,6 @@
tlbgwr
tlbinv
tlbinvf
tlbp
tlbr
tlbwi
tlbwr
trunc.l.d $f23,$f23
trunc.l.s $f28,$f31
wrpgpr $zero,$t5

4
test/MC/Mips/mips32r2/valid.s
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@ -161,6 +161,10 @@
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
tlti $t6,-21059
tltiu $ra,-5076
tnei $t4,-29647

4
test/MC/Mips/mips4/valid-xfail.s
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@ -47,7 +47,3 @@
recip.s $f3,$f30
rsqrt.d $f3,$f28
rsqrt.s $f4,$f8
tlbp
tlbr
tlbwi
tlbwr

4
test/MC/Mips/mips4/valid.s
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@ -177,6 +177,10 @@
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
tlti $t6,-21059
tltiu $ra,-5076
tnei $t4,-29647

4
test/MC/Mips/mips5/valid-xfail.s
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@ -85,7 +85,3 @@
rsqrt.d $f3,$f28
rsqrt.s $f4,$f8
sub.ps $f5,$f14,$f26
tlbp
tlbr
tlbwi
tlbwr

4
test/MC/Mips/mips5/valid.s
View File

@ -177,6 +177,10 @@
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
tlti $t6,-21059
tltiu $ra,-5076
tnei $t4,-29647

4
test/MC/Mips/mips64/valid-xfail.s
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@ -92,7 +92,3 @@
rsqrt.d $f3,$f28
rsqrt.s $f4,$f8
sub.ps $f5,$f14,$f26
tlbp
tlbr
tlbwi
tlbwr

4
test/MC/Mips/mips64/valid.s
View File

@ -191,6 +191,10 @@
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
tlti $t6,-21059
tltiu $ra,-5076
tnei $t4,-29647

4
test/MC/Mips/mips64r2/valid-xfail.s
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@ -306,10 +306,6 @@
tlbgwr
tlbinv
tlbinvf
tlbp
tlbr
tlbwi
tlbwr
wrpgpr $zero,$t5
xor.v $w20,$w21,$w30
yield $v1,$s0

4
test/MC/Mips/mips64r2/valid.s
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@ -213,6 +213,10 @@
teqi $s5,-17504
tgei $s1,5025
tgeiu $sp,-28621
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
tlti $t6,-21059
tltiu $ra,-5076
tnei $t4,-29647