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AMDGPU: Remove SCCReg.

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These should be handled as a physical register rather
than a virtual register class with one member.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244061 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2015-08-05 16:42:54 +00:00
parent 22c5f2a36e
commit de67abf186
5 changed files with 22 additions and 36 deletions
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2
lib/Target/AMDGPU/SIInstrFormats.td
View File

@ -249,13 +249,13 @@ class SOP2 <dag outs, dag ins, string asm, list<dag> pattern> :
class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
InstSI<outs, ins, asm, pattern>, SOPCe <op> {
let DisableEncoding = "$dst";
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let SALU = 1;
let SOPC = 1;
let isCodeGenOnly = 0;
let Defs = [SCC];
let UseNamedOperandTable = 1;
}

40
lib/Target/AMDGPU/SIInstrInfo.td
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@ -393,7 +393,7 @@ def GDS01MatchClass : GDSBaseMatchClass <"parseDSOff01OptionalOps">;
class GLCBaseMatchClass <string parser> : AsmOperandClass {
let Name = "GLC"#parser;
let PredicateMethod = "isImm";
let ParserMethod = parser;
let ParserMethod = parser;
let RenderMethod = "addImmOperands";
}
@ -717,19 +717,6 @@ class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
let AssemblerPredicates = [isVI];
}
multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
(ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
(ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
opName#" $dst, $src0, $src1 [$scc]">;
def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
(ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
opName#" $dst, $src0, $src1 [$scc]">;
}
multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
list<dag> pattern> {
@ -758,8 +745,10 @@ multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
string opName, PatLeaf cond> : SOPC <
op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
opName#" $src0, $src1", []>;
op, (outs), (ins rc:$src0, rc:$src1),
opName#" $src0, $src1", []> {
let Defs = [SCC];
}
class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
: SOPC_Helper<op, SSrc_32, i32, opName, cond>;
@ -812,15 +801,20 @@ multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
}
multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
(ins SReg_32:$src0, u16imm:$src1), pattern>;
def "" : SOPK_Pseudo <opName, (outs),
(ins SReg_32:$src0, u16imm:$src1), pattern> {
let Defs = [SCC];
}
let DisableEncoding = "$dst" in {
def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
(ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16">;
def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
(ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16">;
def _si : SOPK_Real_si <op, opName, (outs),
(ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16"> {
let Defs = [SCC];
}
def _vi : SOPK_Real_vi <op, opName, (outs),
(ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16"> {
let Defs = [SCC];
}
}

8
lib/Target/AMDGPU/SIInstructions.td
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@ -438,16 +438,16 @@ def S_BRANCH : SOPP <
let isBarrier = 1;
}
let DisableEncoding = "$scc" in {
let Uses = [SCC] in {
def S_CBRANCH_SCC0 : SOPP <
0x00000004, (ins sopp_brtarget:$simm16, SCCReg:$scc),
0x00000004, (ins sopp_brtarget:$simm16),
"s_cbranch_scc0 $simm16"
>;
def S_CBRANCH_SCC1 : SOPP <
0x00000005, (ins sopp_brtarget:$simm16, SCCReg:$scc),
0x00000005, (ins sopp_brtarget:$simm16),
"s_cbranch_scc1 $simm16"
>;
} // End DisableEncoding = "$scc"
} // End Uses = [SCC]
def S_CBRANCH_VCCZ : SOPP <
0x00000006, (ins sopp_brtarget:$simm16, VCCReg:$vcc),

2
lib/Target/AMDGPU/SIRegisterInfo.cpp
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@ -372,8 +372,6 @@ const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass(
const TargetRegisterClass *SRC) const {
if (hasVGPRs(SRC)) {
return SRC;
} else if (SRC == &AMDGPU::SCCRegRegClass) {
return &AMDGPU::VCCRegRegClass;
} else if (getCommonSubClass(SRC, &AMDGPU::SGPR_32RegClass)) {
return &AMDGPU::VGPR_32RegClass;
} else if (getCommonSubClass(SRC, &AMDGPU::SGPR_64RegClass)) {

6
lib/Target/AMDGPU/SIRegisterInfo.td
View File

@ -182,12 +182,6 @@ class RegImmMatcher<string name> : AsmOperandClass {
let RenderMethod = "addRegOrImmOperands";
}
// Special register classes for predicates and the M0 register
def SCCReg : RegisterClass<"AMDGPU", [i32, i1], 32, (add SCC)> {
let CopyCost = -1; // Theoretically it is possible to read from SCC,
// but it should never be necessary.
}
def VCCReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add VCC)>;
def EXECReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add EXEC)>;