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[NVPTX] Add support for isspacep instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211931 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -889,6 +889,24 @@ def int_nvvm_compiler_error :
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def int_nvvm_compiler_warn :
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Intrinsic<[], [llvm_anyptr_ty], [], "llvm.nvvm.compiler.warn">;
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// isspacep.{const, global, local, shared}
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def int_nvvm_isspacep_const
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: Intrinsic<[llvm_i1_ty], [llvm_ptr_ty], [IntrNoMem],
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"llvm.nvvm.isspacep.const">,
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GCCBuiltin<"__nvvm_isspacep_const">;
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def int_nvvm_isspacep_global
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: Intrinsic<[llvm_i1_ty], [llvm_ptr_ty], [IntrNoMem],
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"llvm.nvvm.isspacep.global">,
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GCCBuiltin<"__nvvm_isspacep_global">;
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def int_nvvm_isspacep_local
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: Intrinsic<[llvm_i1_ty], [llvm_ptr_ty], [IntrNoMem],
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"llvm.nvvm.isspacep.local">,
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GCCBuiltin<"__nvvm_isspacep_local">;
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def int_nvvm_isspacep_shared
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: Intrinsic<[llvm_i1_ty], [llvm_ptr_ty], [IntrNoMem],
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"llvm.nvvm.isspacep.shared">,
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GCCBuiltin<"__nvvm_isspacep_shared">;
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// Environment register read
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def int_nvvm_read_ptx_sreg_envreg0
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: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
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@ -161,6 +161,8 @@ def hasHWROT32 : Predicate<"Subtarget.hasHWROT32()">;
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def true : Predicate<"1">;
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def hasPTX31 : Predicate<"Subtarget.getPTXVersion() >= 31">;
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//===----------------------------------------------------------------------===//
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// Some Common Instruction Class Templates
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@ -1689,6 +1689,44 @@ def INT_NVVM_COMPILER_ERROR_64 : NVPTXInst<(outs), (ins Int64Regs:$a),
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[(int_nvvm_compiler_error Int64Regs:$a)]>;
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// isspacep
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def ISSPACEP_CONST_32
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: NVPTXInst<(outs Int1Regs:$d), (ins Int32Regs:$a),
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"isspacep.const \t$d, $a;",
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[(set Int1Regs:$d, (int_nvvm_isspacep_const Int32Regs:$a))]>,
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Requires<[hasPTX31]>;
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def ISSPACEP_CONST_64
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: NVPTXInst<(outs Int1Regs:$d), (ins Int64Regs:$a),
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"isspacep.const \t$d, $a;",
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[(set Int1Regs:$d, (int_nvvm_isspacep_const Int64Regs:$a))]>,
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Requires<[hasPTX31]>;
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def ISSPACEP_GLOBAL_32
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: NVPTXInst<(outs Int1Regs:$d), (ins Int32Regs:$a),
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"isspacep.global \t$d, $a;",
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[(set Int1Regs:$d, (int_nvvm_isspacep_global Int32Regs:$a))]>;
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def ISSPACEP_GLOBAL_64
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: NVPTXInst<(outs Int1Regs:$d), (ins Int64Regs:$a),
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"isspacep.global \t$d, $a;",
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[(set Int1Regs:$d, (int_nvvm_isspacep_global Int64Regs:$a))]>;
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def ISSPACEP_LOCAL_32
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: NVPTXInst<(outs Int1Regs:$d), (ins Int32Regs:$a),
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"isspacep.local \t$d, $a;",
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[(set Int1Regs:$d, (int_nvvm_isspacep_local Int32Regs:$a))]>;
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def ISSPACEP_LOCAL_64
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: NVPTXInst<(outs Int1Regs:$d), (ins Int64Regs:$a),
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"isspacep.local \t$d, $a;",
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[(set Int1Regs:$d, (int_nvvm_isspacep_local Int64Regs:$a))]>;
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def ISSPACEP_SHARED_32
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: NVPTXInst<(outs Int1Regs:$d), (ins Int32Regs:$a),
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"isspacep.shared \t$d, $a;",
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[(set Int1Regs:$d, (int_nvvm_isspacep_shared Int32Regs:$a))]>;
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def ISSPACEP_SHARED_64
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: NVPTXInst<(outs Int1Regs:$d), (ins Int64Regs:$a),
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"isspacep.shared \t$d, $a;",
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[(set Int1Regs:$d, (int_nvvm_isspacep_shared Int64Regs:$a))]>;
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// Special register reads
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def MOV_SPECIAL : NVPTXInst<(outs Int32Regs:$d),
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(ins SpecialRegs:$r),
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35
test/CodeGen/NVPTX/isspacep.ll
Normal file
35
test/CodeGen/NVPTX/isspacep.ll
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@ -0,0 +1,35 @@
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
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declare i1 @llvm.nvvm.isspacep.const(i8*) readnone noinline
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declare i1 @llvm.nvvm.isspacep.global(i8*) readnone noinline
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declare i1 @llvm.nvvm.isspacep.local(i8*) readnone noinline
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declare i1 @llvm.nvvm.isspacep.shared(i8*) readnone noinline
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; CHECK: is_const
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define i1 @is_const(i8* %addr) {
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; CHECK: isspacep.const
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%v = tail call i1 @llvm.nvvm.isspacep.const(i8* %addr)
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ret i1 %v
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}
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; CHECK: is_global
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define i1 @is_global(i8* %addr) {
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; CHECK: isspacep.global
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%v = tail call i1 @llvm.nvvm.isspacep.global(i8* %addr)
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ret i1 %v
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}
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; CHECK: is_local
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define i1 @is_local(i8* %addr) {
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; CHECK: isspacep.local
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%v = tail call i1 @llvm.nvvm.isspacep.local(i8* %addr)
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ret i1 %v
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}
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; CHECK: is_shared
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define i1 @is_shared(i8* %addr) {
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; CHECK: isspacep.shared
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%v = tail call i1 @llvm.nvvm.isspacep.shared(i8* %addr)
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ret i1 %v
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}
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