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MachineVerifier: Allow undef reads if a matching superreg is defined.
Summary: Some pseudo instruction expansions break down a wide register use into multiple uses of smaller sub registers. If the super register was partially undefined the broken down sub registers may be completely undefined now leading to MachineVerifier complaints. Unfortunately liveness information to add the required dead flags is not easily (cheaply) available when expanding pseudo instructions. This commit changes the verifier to be quiet if there is an additional implicit use of a super register. Pseudo instruction expanders can use this to mark cases where partially defined values get potentially broken into completely undefined ones. Differential Revision: http://reviews.llvm.org/D6973 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226047 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1077,6 +1077,25 @@ void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
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}
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}
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}
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// If there is an additional implicit-use of a super register we stop
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// here. By definition we are fine if the super register is not
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// (completely) dead, if the complete super register is dead we will
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// get a report for its operand.
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if (Bad) {
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for (const MachineOperand &MOP : MI->uses()) {
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if (!MOP.isReg())
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continue;
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if (!MOP.isImplicit())
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continue;
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for (MCSubRegIterator SubRegs(MOP.getReg(), TRI); SubRegs.isValid();
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++SubRegs) {
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if (*SubRegs == Reg) {
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Bad = false;
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break;
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}
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}
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}
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}
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if (Bad)
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report("Using an undefined physical register", MO, MONum);
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} else if (MRI->def_empty(Reg)) {
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