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[mips][microMIPS] Implement PREFX, LHUE, LBE, LBUE, LHE, LWE, SBE, SHE and SWE instructions
Differential Revision: http://reviews.llvm.org/D9189 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247780 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zoran Jovanovic
parent
217d6318e4
commit
de9de11b23
@ -947,6 +947,10 @@ public:
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return isMem() && isConstantMemOff() && isInt<Bits>(getConstantMemOff())
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&& getMemBase()->isGPRAsmReg();
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}
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template <unsigned Bits> bool isMemWithSimmOffsetGPR() const {
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return isMem() && isConstantMemOff() && isInt<Bits>(getConstantMemOff()) &&
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getMemBase()->isGPRAsmReg();
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}
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bool isMemWithGRPMM16Base() const {
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return isMem() && getMemBase()->isMM16AsmReg();
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}
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@ -1758,6 +1762,7 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
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if (Imm < 0 || Imm > 60 || (Imm % 4 != 0))
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return Error(IDLoc, "immediate operand value out of range");
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break;
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case Mips::PREFX_MM:
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case Mips::CACHE:
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case Mips::PREF:
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Opnd = Inst.getOperand(2);
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@ -389,6 +389,22 @@ class LW_FM_MM<bits<6> op> : MMArch {
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let Inst{15-0} = addr{15-0};
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}
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class POOL32C_LHUE_FM_MM<bits<6> op, bits<4> fmt, bits<3> funct> : MMArch {
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bits<5> rt;
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bits<21> addr;
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bits<5> base = addr{20-16};
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bits<9> offset = addr{8-0};
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bits<32> Inst;
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let Inst{31-26} = op;
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let Inst{25-21} = rt;
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let Inst{20-16} = base;
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let Inst{15-12} = fmt;
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let Inst{11-9} = funct;
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let Inst{8-0} = offset;
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}
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class LWL_FM_MM<bits<4> funct> {
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bits<5> rt;
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bits<21> addr;
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@ -938,6 +954,21 @@ class CACHE_PREFE_FM_MM<bits<6> op, bits<3> funct> : MMArch {
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let Inst{8-0} = offset;
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}
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class POOL32F_PREFX_FM_MM<bits<6> op, bits<9> funct> : MMArch {
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bits<5> index;
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bits<5> base;
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bits<5> hint;
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bits<32> Inst;
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let Inst{31-26} = op;
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let Inst{25-21} = index;
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let Inst{20-16} = base;
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let Inst{15-11} = hint;
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let Inst{10-9} = 0x0;
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let Inst{8-0} = funct;
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}
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class BARRIER_FM_MM<bits<5> op> : MMArch {
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bits<32> Inst;
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@ -484,6 +484,10 @@ class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
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InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
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!strconcat(opstr, "\t$rd, ${index}(${base})"), [], Itin, FrmFI>;
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class PrefetchIndexed<string opstr> :
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InstSE<(outs), (ins PtrRC:$base, PtrRC:$index, uimm5:$hint),
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!strconcat(opstr, "\t$hint, ${index}(${base})"), [], NoItinerary, FrmOther>;
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class AddImmUPC<string opstr, RegisterOperand RO> :
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InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm),
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!strconcat(opstr, "\t$rs, $imm"), [], NoItinerary, FrmR>;
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@ -713,6 +717,18 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
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}
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let DecoderMethod = "DecodeMemMMImm9" in {
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def LBE_MM : Load<"lbe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>;
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def LBuE_MM : Load<"lbue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>;
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def LHE_MM : Load<"lhe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>;
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def LHuE_MM : Load<"lhue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>;
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def LWE_MM : Load<"lwe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>;
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def SBE_MM : Store<"sbe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>;
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def SHE_MM : Store<"she", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>;
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def SWE_MM : StoreMemory<"swe", GPR32Opnd, mem_simm9gpr>,
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POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>;
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}
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def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
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def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
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@ -890,6 +906,8 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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def SDBBP_MM : MMRel, SYS_FT<"sdbbp">, SDBBP_FM_MM;
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def RDHWR_MM : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM_MM;
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def PREFX_MM : PrefetchIndexed<"prefx">, POOL32F_PREFX_FM_MM<0x15, 0x1A0>;
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}
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let Predicates = [InMicroMips] in {
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@ -466,6 +466,14 @@ def MipsMemSimm9AsmOperand : AsmOperandClass {
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let PredicateMethod = "isMemWithSimmOffset<9>";
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}
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def MipsMemSimm9GPRAsmOperand : AsmOperandClass {
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let Name = "MemOffsetSimm9GPR";
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let SuperClasses = [MipsMemAsmOperand];
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let RenderMethod = "addMemOperands";
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let ParserMethod = "parseMemOperand";
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let PredicateMethod = "isMemWithSimmOffsetGPR<9>";
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}
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def MipsMemSimm11AsmOperand : AsmOperandClass {
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let Name = "MemOffsetSimm11";
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let SuperClasses = [MipsMemAsmOperand];
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@ -519,6 +527,12 @@ def mem_simm9 : mem_generic {
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let ParserMatchClass = MipsMemSimm9AsmOperand;
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}
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def mem_simm9gpr : mem_generic {
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let MIOperandInfo = (ops ptr_rc, simm9);
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let EncoderMethod = "getMemEncoding";
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let ParserMatchClass = MipsMemSimm9GPRAsmOperand;
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}
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def mem_simm11 : mem_generic {
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let MIOperandInfo = (ops ptr_rc, simm11);
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let EncoderMethod = "getMemEncoding";
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@ -707,14 +721,19 @@ class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
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let mayLoad = 1;
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}
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class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
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class StoreMemory<string opstr, DAGOperand RO, DAGOperand MO,
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SDPatternOperator OpNode = null_frag,
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InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
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InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
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InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
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[(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
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let DecoderMethod = "DecodeMem";
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let mayStore = 1;
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}
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class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
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InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
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StoreMemory<opstr, RO, mem, OpNode, Itin, Addr>;
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// Load/Store Left/Right
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let canFoldAsLoad = 1 in
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class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
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@ -346,3 +346,21 @@
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0x60 0x25 0xa6 0x08 # CHECK: cachee 1, 8($5)
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0x60 0x25 0xa4 0x08 # CHECK: prefe 1, 8($5)
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0x54 0x65 0x09 0xa0 # CHECK: prefx 1, $3($5)
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0x60 0x82 0x62 0x08 # CHECK: lhue $4, 8($2)
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0x60 0x82 0x68 0x08 # CHECK: lbe $4, 8($2)
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0x60 0x82 0x60 0x08 # CHECK: lbue $4, 8($2)
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0x60 0x82 0x6a 0x08 # CHECK: lhe $4, 8($2)
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0x60 0x82 0x6e 0x08 # CHECK: lwe $4, 8($2)
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0x60 0xa4 0xa8 0x08 # CHECK: sbe $5, 8($4)
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0x60 0xa4 0xaa 0x08 # CHECK: she $5, 8($4)
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0x60 0xa4 0xae 0x08 # CHECK: swe $5, 8($4)
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@ -346,3 +346,21 @@
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0x25 0x60 0x08 0xa6 # CHECK: cachee 1, 8($5)
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0x25 0x60 0x08 0xa4 # CHECK: prefe 1, 8($5)
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0x65 0x54 0xa0 0x09 # CHECK: prefx 1, $3($5)
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0x82 0x60 0x08 0x62 # CHECK: lhue $4, 8($2)
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0x82 0x60 0x08 0x68 # CHECK: lbe $4, 8($2)
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0x82 0x60 0x08 0x60 # CHECK: lbue $4, 8($2)
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0x82 0x60 0x08 0x6a # CHECK: lhe $4, 8($2)
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0x82 0x60 0x08 0x6e # CHECK: lwe $4, 8($2)
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0xa4 0x60 0x08 0xa8 # CHECK: sbe $5, 8($4)
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0xa4 0x60 0x08 0xaa # CHECK: she $5, 8($4)
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0xa4 0x60 0x08 0xae # CHECK: swe $5, 8($4)
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@ -41,6 +41,7 @@
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# CHECK-EL: tlbwr # encoding: [0x00,0x00,0x7c,0x33]
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# CHECK-EL: prefe 1, 8($5) # encoding: [0x25,0x60,0x08,0xa4]
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# CHECK-EL: cachee 1, 8($5) # encoding: [0x25,0x60,0x08,0xa6]
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# CHECK-EL: prefx 1, $3($5) # encoding: [0x65,0x54,0xa0,0x09]
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#------------------------------------------------------------------------------
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# Big endian
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#------------------------------------------------------------------------------
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@ -76,6 +77,7 @@
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# CHECK-EB: tlbwr # encoding: [0x00,0x00,0x33,0x7c]
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# CHECK-EB: prefe 1, 8($5) # encoding: [0x60,0x25,0xa4,0x08]
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# CHECK-EB: cachee 1, 8($5) # encoding: [0x60,0x25,0xa6,0x08]
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# CHECK-EB: prefx 1, $3($5) # encoding: [0x54,0x65,0x09,0xa0]
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sdbbp
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sdbbp 34
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@ -106,3 +108,4 @@
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tlbwr
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prefe 1, 8($5)
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cachee 1, 8($5)
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prefx 1, $3($5)
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@ -78,3 +78,4 @@
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break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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wait 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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prefx 33, $8($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
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@ -44,6 +44,14 @@
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# CHECK-EL: swm32 $16, $17, 8($sp) # encoding: [0x5d,0x20,0x08,0xd0]
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# CHECK-EL: swp $16, 8($4) # encoding: [0x04,0x22,0x08,0x90]
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# CHECK-EL: lwp $16, 8($4) # encoding: [0x04,0x22,0x08,0x10]
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# CHECK-EL: lhue $4, 8($2) # encoding: [0x82,0x60,0x08,0x62]
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# CHECK-EL: lbe $4, 8($2) # encoding: [0x82,0x60,0x08,0x68]
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# CHECK-EL: lbue $4, 8($2) # encoding: [0x82,0x60,0x08,0x60]
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# CHECK-EL: lhe $4, 8($2) # encoding: [0x82,0x60,0x08,0x6a]
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# CHECK-EL: lwe $4, 8($2) # encoding: [0x82,0x60,0x08,0x6e]
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# CHECK-EL: sbe $5, 8($4) # encoding: [0xa4,0x60,0x08,0xa8]
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# CHECK-EL: she $5, 8($4) # encoding: [0xa4,0x60,0x08,0xaa]
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# CHECK-EL: swe $5, 8($4) # encoding: [0xa4,0x60,0x08,0xae]
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#------------------------------------------------------------------------------
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# Big endian
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#------------------------------------------------------------------------------
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@ -82,6 +90,14 @@
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# CHECK-EB: swm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0xd0,0x08]
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# CHECK-EB: swp $16, 8($4) # encoding: [0x22,0x04,0x90,0x08]
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# CHECK-EB: lwp $16, 8($4) # encoding: [0x22,0x04,0x10,0x08]
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# CHECK-EB: lhue $4, 8($2) # encoding: [0x60,0x82,0x62,0x08]
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# CHECK-EB: lbe $4, 8($2) # encoding: [0x60,0x82,0x68,0x08]
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# CHECK-EB: lbue $4, 8($2) # encoding: [0x60,0x82,0x60,0x08]
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# CHECK-EB: lhe $4, 8($2) # encoding: [0x60,0x82,0x6a,0x08]
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# CHECK-EB: lwe $4, 8($2) # encoding: [0x60,0x82,0x6e,0x08]
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# CHECK-EB: sbe $5, 8($4) # encoding: [0x60,0xa4,0xa8,0x08]
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# CHECK-EB: she $5, 8($4) # encoding: [0x60,0xa4,0xaa,0x08]
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# CHECK-EB: swe $5, 8($4) # encoding: [0x60,0xa4,0xae,0x08]
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lb $5, 8($4)
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lbu $6, 8($4)
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lh $2, 8($4)
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@ -117,3 +133,11 @@
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swm $16, $17, 8($sp)
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swp $16, 8($4)
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lwp $16, 8($4)
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lhue $4, 8($2)
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lbe $4, 8($2)
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lbue $4, 8($2)
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lhe $4, 8($2)
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lwe $4, 8($2)
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sbe $5, 8($4)
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she $5, 8($4)
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swe $5, 8($4)
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@ -8,4 +8,3 @@
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.set noat
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bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
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bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
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prefx 0,$2($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
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@ -11,3 +11,4 @@
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lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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swxc1 $f19,$12($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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prefx 0,$2($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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@ -8,4 +8,3 @@
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.set noat
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bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
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bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
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prefx 0,$2($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
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@ -14,3 +14,4 @@
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lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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swxc1 $f19,$12($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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prefx 0,$2($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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