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Fix sfence, lfence, mfence, and clflush to be able to be selected when AVX is enabled. Fix monitor and mwait to require SSE3 or AVX, previously they worked even if SSE3 was disabled. Make prefetch instructions not set the execution domain since they don't use XMM registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147409 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
8943574b44
commit
de9e4c728e
@ -339,10 +339,6 @@ class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedSingle>, TB,
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Requires<[HasAVX]>;
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class VoPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
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Requires<[HasXMM]>;
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// SSE2 Instruction Templates:
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//
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@ -475,6 +475,7 @@ def HasAVX : Predicate<"Subtarget->hasAVX()">;
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def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
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def HasXMM : Predicate<"Subtarget->hasXMM()">;
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def HasXMMInt : Predicate<"Subtarget->hasXMMInt()">;
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def HasSSE3orAVX : Predicate<"Subtarget->hasSSE3orAVX()">;
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def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
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def HasAES : Predicate<"Subtarget->hasAES()">;
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@ -3253,19 +3253,21 @@ def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
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//===----------------------------------------------------------------------===//
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// Prefetch intrinsic.
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def PREFETCHT0 : VoPSI<0x18, MRM1m, (outs), (ins i8mem:$src),
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"prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>;
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def PREFETCHT1 : VoPSI<0x18, MRM2m, (outs), (ins i8mem:$src),
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"prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>;
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def PREFETCHT2 : VoPSI<0x18, MRM3m, (outs), (ins i8mem:$src),
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"prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>;
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def PREFETCHNTA : VoPSI<0x18, MRM0m, (outs), (ins i8mem:$src),
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"prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>;
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let Predicates = [HasXMM] in {
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def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
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"prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>, TB;
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def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
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"prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>, TB;
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def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
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"prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>, TB;
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def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
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"prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>, TB;
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}
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// Flush cache
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def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
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"clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
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TB, Requires<[HasSSE2]>;
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TB, Requires<[HasXMMInt]>;
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// Pause. This "instruction" is encoded as "rep; nop", so even though it
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// was introduced with SSE2, it's backward compatible.
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@ -3273,11 +3275,11 @@ def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
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// Load, store, and memory fence
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def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
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"sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
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"sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasXMM]>;
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def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
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"lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
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"lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasXMMInt]>;
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def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
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"mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
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"mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasXMMInt]>;
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def : Pat<(X86SFence), (SFENCE)>;
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def : Pat<(X86LFence), (LFENCE)>;
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@ -5463,17 +5465,19 @@ def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
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let usesCustomInserter = 1 in {
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def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
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[(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>;
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[(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
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Requires<[HasSSE3orAVX]>;
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def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
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[(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>;
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[(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>,
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Requires<[HasSSE3orAVX]>;
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}
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let Uses = [EAX, ECX, EDX] in
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def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
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Requires<[HasSSE3]>;
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Requires<[HasSSE3orAVX]>;
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let Uses = [ECX, EAX] in
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def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
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Requires<[HasSSE3]>;
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Requires<[HasSSE3orAVX]>;
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def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
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def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
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@ -1,5 +1,5 @@
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; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s -check-prefix=WIN64
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; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse3 | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse3 | FileCheck %s -check-prefix=WIN64
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; PR8573
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; CHECK: foo:
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@ -2481,4 +2481,52 @@ define void @test_x86_avx_vzeroupper() {
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}
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declare void @llvm.x86.avx.vzeroupper() nounwind
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; Make sure instructions with no AVX equivalents, but are associated with SSEX feature flags still work
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; CHECK: monitor
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define void @monitor(i8* %P, i32 %E, i32 %H) nounwind {
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entry:
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tail call void @llvm.x86.sse3.monitor(i8* %P, i32 %E, i32 %H)
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ret void
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}
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declare void @llvm.x86.sse3.monitor(i8*, i32, i32) nounwind
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; CHECK: mwait
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define void @mwait(i32 %E, i32 %H) nounwind {
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entry:
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tail call void @llvm.x86.sse3.mwait(i32 %E, i32 %H)
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ret void
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}
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declare void @llvm.x86.sse3.mwait(i32, i32) nounwind
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; CHECK: sfence
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define void @sfence() nounwind {
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entry:
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tail call void @llvm.x86.sse.sfence()
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ret void
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}
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declare void @llvm.x86.sse.sfence() nounwind
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; CHECK: lfence
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define void @lfence() nounwind {
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entry:
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tail call void @llvm.x86.sse2.lfence()
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ret void
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}
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declare void @llvm.x86.sse2.lfence() nounwind
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; CHECK: mfence
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define void @mfence() nounwind {
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entry:
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tail call void @llvm.x86.sse2.mfence()
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ret void
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}
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declare void @llvm.x86.sse2.mfence() nounwind
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; CHECK: clflush
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define void @clflush(i8* %p) nounwind {
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entry:
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tail call void @llvm.x86.sse2.clflush(i8* %p)
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ret void
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}
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declare void @llvm.x86.sse2.clflush(i8*) nounwind
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