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[AArch64]Add patterns to match normal shift nodes: shl, sra and srl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197969 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hao Liu
parent
4905226c1c
commit
dfe4fd9ceb
@ -8662,6 +8662,61 @@ def SHA1C : NeonI_Cryptosha3_qsv<0b00, 0b000, "sha1c", int_aarch64_neon_sha1c>;
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def SHA1P : NeonI_Cryptosha3_qsv<0b00, 0b001, "sha1p", int_aarch64_neon_sha1p>;
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def SHA1M : NeonI_Cryptosha3_qsv<0b00, 0b010, "sha1m", int_aarch64_neon_sha1m>;
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// Additional patterns to match shl to USHL.
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def : Pat<(v8i8 (shl (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
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(USHLvvv_8B $Rn, $Rm)>;
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def : Pat<(v4i16 (shl (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
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(USHLvvv_4H $Rn, $Rm)>;
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def : Pat<(v2i32 (shl (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
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(USHLvvv_2S $Rn, $Rm)>;
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def : Pat<(v1i64 (shl (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
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(USHLddd $Rn, $Rm)>;
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def : Pat<(v16i8 (shl (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
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(USHLvvv_16B $Rn, $Rm)>;
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def : Pat<(v8i16 (shl (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
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(USHLvvv_8H $Rn, $Rm)>;
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def : Pat<(v4i32 (shl (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
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(USHLvvv_4S $Rn, $Rm)>;
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def : Pat<(v2i64 (shl (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
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(USHLvvv_2D $Rn, $Rm)>;
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// Additional patterns to match sra, srl.
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// For a vector right shift by vector, the shift amounts of SSHL/USHL are
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// negative. Negate the vector of shift amount first.
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def : Pat<(v8i8 (srl (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
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(USHLvvv_8B $Rn, (NEG8b $Rm))>;
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def : Pat<(v4i16 (srl (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
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(USHLvvv_4H $Rn, (NEG4h $Rm))>;
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def : Pat<(v2i32 (srl (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
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(USHLvvv_2S $Rn, (NEG2s $Rm))>;
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def : Pat<(v1i64 (srl (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
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(USHLddd $Rn, (NEGdd $Rm))>;
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def : Pat<(v16i8 (srl (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
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(USHLvvv_16B $Rn, (NEG16b $Rm))>;
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def : Pat<(v8i16 (srl (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
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(USHLvvv_8H $Rn, (NEG8h $Rm))>;
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def : Pat<(v4i32 (srl (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
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(USHLvvv_4S $Rn, (NEG4s $Rm))>;
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def : Pat<(v2i64 (srl (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
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(USHLvvv_2D $Rn, (NEG2d $Rm))>;
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def : Pat<(v8i8 (sra (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
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(SSHLvvv_8B $Rn, (NEG8b $Rm))>;
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def : Pat<(v4i16 (sra (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
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(SSHLvvv_4H $Rn, (NEG4h $Rm))>;
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def : Pat<(v2i32 (sra (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
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(SSHLvvv_2S $Rn, (NEG2s $Rm))>;
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def : Pat<(v1i64 (sra (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
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(SSHLddd $Rn, (NEGdd $Rm))>;
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def : Pat<(v16i8 (sra (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
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(SSHLvvv_16B $Rn, (NEG16b $Rm))>;
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def : Pat<(v8i16 (sra (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
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(SSHLvvv_8H $Rn, (NEG8h $Rm))>;
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def : Pat<(v4i32 (sra (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
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(SSHLvvv_4S $Rn, (NEG4s $Rm))>;
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def : Pat<(v2i64 (sra (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
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(SSHLvvv_2D $Rn, (NEG2d $Rm))>;
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//
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// Patterns for handling half-precision values
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//
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185
test/CodeGen/AArch64/neon-shl-ashr-lshr.ll
Normal file
185
test/CodeGen/AArch64/neon-shl-ashr-lshr.ll
Normal file
@ -0,0 +1,185 @@
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; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
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define <8 x i8> @shl.v8i8(<8 x i8> %a, <8 x i8> %b) {
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; CHECK-LABEL: shl.v8i8:
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; CHECK: ushl v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
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%c = shl <8 x i8> %a, %b
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ret <8 x i8> %c
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}
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define <4 x i16> @shl.v4i16(<4 x i16> %a, <4 x i16> %b) {
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; CHECK-LABEL: shl.v4i16:
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; CHECK: ushl v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
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%c = shl <4 x i16> %a, %b
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ret <4 x i16> %c
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}
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define <2 x i32> @shl.v2i32(<2 x i32> %a, <2 x i32> %b) {
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; CHECK-LABEL: shl.v2i32:
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; CHECK: ushl v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
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%c = shl <2 x i32> %a, %b
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ret <2 x i32> %c
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}
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define <1 x i64> @shl.v1i64(<1 x i64> %a, <1 x i64> %b) {
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; CHECK-LABEL: shl.v1i64:
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; CHECK: ushl d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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%c = shl <1 x i64> %a, %b
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ret <1 x i64> %c
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}
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define <16 x i8> @shl.v16i8(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: shl.v16i8:
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; CHECK: ushl v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
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%c = shl <16 x i8> %a, %b
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ret <16 x i8> %c
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}
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define <8 x i16> @shl.v8i16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: shl.v8i16:
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; CHECK: ushl v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h
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%c = shl <8 x i16> %a, %b
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ret <8 x i16> %c
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}
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define <4 x i32> @shl.v4i32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: shl.v4i32:
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; CHECK: ushl v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
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%c = shl <4 x i32> %a, %b
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ret <4 x i32> %c
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}
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define <2 x i64> @shl.v2i64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: shl.v2i64:
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; CHECK: ushl v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
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%c = shl <2 x i64> %a, %b
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ret <2 x i64> %c
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}
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define <8 x i8> @lshr.v8i8(<8 x i8> %a, <8 x i8> %b) {
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; CHECK-LABEL: lshr.v8i8:
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; CHECK: neg v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
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; CHECK: ushl v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
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%c = lshr <8 x i8> %a, %b
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ret <8 x i8> %c
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}
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define <4 x i16> @lshr.v4i16(<4 x i16> %a, <4 x i16> %b) {
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; CHECK-LABEL: lshr.v4i16:
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; CHECK: neg v{{[0-9]+}}.4h, v{{[0-9]+}}.4
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; CHECK: ushl v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
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%c = lshr <4 x i16> %a, %b
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ret <4 x i16> %c
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}
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define <2 x i32> @lshr.v2i32(<2 x i32> %a, <2 x i32> %b) {
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; CHECK-LABEL: lshr.v2i32:
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; CHECK: neg v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
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; CHECK: ushl v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
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%c = lshr <2 x i32> %a, %b
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ret <2 x i32> %c
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}
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define <1 x i64> @lshr.v1i64(<1 x i64> %a, <1 x i64> %b) {
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; CHECK-LABEL: lshr.v1i64:
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; CHECK: neg d{{[0-9]+}}, d{{[0-9]+}}
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; CHECK: ushl d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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%c = lshr <1 x i64> %a, %b
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ret <1 x i64> %c
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}
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define <16 x i8> @lshr.v16i8(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: lshr.v16i8:
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; CHECK: neg v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
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; CHECK: ushl v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
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%c = lshr <16 x i8> %a, %b
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ret <16 x i8> %c
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}
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define <8 x i16> @lshr.v8i16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: lshr.v8i16:
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; CHECK: neg v{{[0-9]+}}.8h, v{{[0-9]+}}.8h
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; CHECK: ushl v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h
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%c = lshr <8 x i16> %a, %b
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ret <8 x i16> %c
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}
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define <4 x i32> @lshr.v4i32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: lshr.v4i32:
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; CHECK: neg v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
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; CHECK: ushl v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
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%c = lshr <4 x i32> %a, %b
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ret <4 x i32> %c
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}
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define <2 x i64> @lshr.v2i64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: lshr.v2i64:
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; CHECK: neg v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
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; CHECK: ushl v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
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%c = lshr <2 x i64> %a, %b
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ret <2 x i64> %c
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}
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define <8 x i8> @ashr.v8i8(<8 x i8> %a, <8 x i8> %b) {
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; CHECK-LABEL: ashr.v8i8:
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; CHECK: neg v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
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; CHECK: sshl v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
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%c = ashr <8 x i8> %a, %b
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ret <8 x i8> %c
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}
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define <4 x i16> @ashr.v4i16(<4 x i16> %a, <4 x i16> %b) {
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; CHECK-LABEL: ashr.v4i16:
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; CHECK: neg v{{[0-9]+}}.4h, v{{[0-9]+}}.4
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; CHECK: sshl v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
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%c = ashr <4 x i16> %a, %b
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ret <4 x i16> %c
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}
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define <2 x i32> @ashr.v2i32(<2 x i32> %a, <2 x i32> %b) {
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; CHECK-LABEL: ashr.v2i32:
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; CHECK: neg v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
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; CHECK: sshl v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
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%c = ashr <2 x i32> %a, %b
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ret <2 x i32> %c
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}
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define <1 x i64> @ashr.v1i64(<1 x i64> %a, <1 x i64> %b) {
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; CHECK-LABEL: ashr.v1i64:
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; CHECK: neg d{{[0-9]+}}, d{{[0-9]+}}
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; CHECK: sshl d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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%c = ashr <1 x i64> %a, %b
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ret <1 x i64> %c
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}
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define <16 x i8> @ashr.v16i8(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: ashr.v16i8:
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; CHECK: neg v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
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; CHECK: sshl v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
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%c = ashr <16 x i8> %a, %b
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ret <16 x i8> %c
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}
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define <8 x i16> @ashr.v8i16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: ashr.v8i16:
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; CHECK: neg v{{[0-9]+}}.8h, v{{[0-9]+}}.8h
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; CHECK: sshl v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h
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%c = ashr <8 x i16> %a, %b
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ret <8 x i16> %c
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}
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define <4 x i32> @ashr.v4i32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: ashr.v4i32:
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; CHECK: neg v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
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; CHECK: sshl v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
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%c = ashr <4 x i32> %a, %b
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ret <4 x i32> %c
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}
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define <2 x i64> @ashr.v2i64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: ashr.v2i64:
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; CHECK: neg v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
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; CHECK: sshl v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
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%c = ashr <2 x i64> %a, %b
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ret <2 x i64> %c
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}
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