Make helper functions/classes/globals static. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228410 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2015-02-06 17:51:54 +00:00
parent 2f2dec87fb
commit e003f1ac8c
8 changed files with 27 additions and 18 deletions

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@ -83,6 +83,8 @@ void StringSaver::anchor() {}
//===----------------------------------------------------------------------===//
namespace {
class CommandLineParser {
public:
// Globals for name and overview of program. Program name is not a string to
@ -190,6 +192,8 @@ public:
void printOptionValues();
};
} // namespace
static ManagedStatic<CommandLineParser> GlobalParser;
void cl::AddLiteralOption(Option &O, const char *Name) {

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@ -186,9 +186,9 @@ static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,
llvm_unreachable("should not be called");
}
bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
CCState &State) {
static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State) {
llvm_unreachable("should not be called");
}

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@ -42,11 +42,15 @@ using namespace llvm;
cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug",
cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden);
cl::opt<bool> UseBitPermRewriter("ppc-use-bit-perm-rewriter", cl::init(true),
cl::desc("use aggressive ppc isel for bit permutations"), cl::Hidden);
cl::opt<bool> BPermRewriterNoMasking("ppc-bit-perm-rewriter-stress-rotates",
cl::desc("stress rotate selection in aggressive ppc isel for "
"bit permutations"), cl::Hidden);
static cl::opt<bool>
UseBitPermRewriter("ppc-use-bit-perm-rewriter", cl::init(true),
cl::desc("use aggressive ppc isel for bit permutations"),
cl::Hidden);
static cl::opt<bool> BPermRewriterNoMasking(
"ppc-bit-perm-rewriter-stress-rotates",
cl::desc("stress rotate selection in aggressive ppc isel for "
"bit permutations"),
cl::Hidden);
namespace llvm {
void initializePPCDAGToDAGISelPass(PassRegistry&);

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@ -88,7 +88,7 @@ namespace {
}
char PPCLoopPreIncPrep::ID = 0;
const char *name = "Prepare loop for pre-inc. addressing modes";
static const char *name = "Prepare loop for pre-inc. addressing modes";
INITIALIZE_PASS_BEGIN(PPCLoopPreIncPrep, DEBUG_TYPE, name, false, false)
INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(ScalarEvolution)

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@ -350,7 +350,7 @@ enum SISubtarget {
VI = 1
};
enum SISubtarget AMDGPUSubtargetToSISubtarget(unsigned Gen) {
static enum SISubtarget AMDGPUSubtargetToSISubtarget(unsigned Gen) {
switch (Gen) {
default:
return SI;

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@ -37,9 +37,10 @@ using namespace llvm;
#define DEBUG_TYPE "x86-cf-opt"
cl::opt<bool> NoX86CFOpt("no-x86-call-frame-opt",
cl::desc("Avoid optimizing x86 call frames for size"),
cl::init(false), cl::Hidden);
static cl::opt<bool>
NoX86CFOpt("no-x86-call-frame-opt",
cl::desc("Avoid optimizing x86 call frames for size"),
cl::init(false), cl::Hidden);
namespace {
class X86CallFrameOptimization : public MachineFunctionPass {

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@ -76,11 +76,11 @@
using namespace llvm;
cl::opt<unsigned> LoopSizeCutoff("irce-loop-size-cutoff", cl::Hidden,
cl::init(64));
static cl::opt<unsigned> LoopSizeCutoff("irce-loop-size-cutoff", cl::Hidden,
cl::init(64));
cl::opt<bool> PrintChangedLoops("irce-print-changed-loops", cl::Hidden,
cl::init(false));
static cl::opt<bool> PrintChangedLoops("irce-print-changed-loops", cl::Hidden,
cl::init(false));
#define DEBUG_TYPE "irce"

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@ -104,7 +104,7 @@ static cl::opt<bool> SkipCounted("spp-counted", cl::init(true));
static cl::opt<bool> SplitBackedge("spp-split-backedge", cl::init(false));
// Print tracing output
cl::opt<bool> TraceLSP("spp-trace", cl::init(false));
static cl::opt<bool> TraceLSP("spp-trace", cl::init(false));
namespace {