Clean up the tablegen descriptions for SparcV8.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11834 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Sparc/Sparc.td

@@ -31,10 +31,7 @@ def SparcV8 : Target {
 
   // According to the Mach-O Runtime ABI, these regs are nonvolatile across
   // calls:
-  let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
+  let CalleeSavedRegisters = [];
-    R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
-    F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
-    F30, F31, CR2, CR3, CR4];
 
   // Pull in Instruction Info:
   let InstructionSet = SparcV8InstrInfo;

lib/Target/Sparc/SparcV8Instrs.td

@@ -1,4 +1,4 @@
-//===- SparcV8InstrInfo.td - Describe the SparcV8 Instruction Set -*- C++ -*-=//
+//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
 // 
 //                     The LLVM Compiler Infrastructure
 //
@@ -7,40 +7,30 @@
 // 
 //===----------------------------------------------------------------------===//
 //
+// This file describes the SparcV8 instructions in TableGen format.
 //
 //===----------------------------------------------------------------------===//
 
-class Format<bits<4> val> {
+include "../Target.td"
-  bits<4> Value = val;
+include "SparcV8Reg.td"
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+class InstV8 : Instruction {          // SparcV8 instruction baseline
+  field bits<32> Inst;
+
+  let Namespace = "V8";
+
+  bits<2> op;
+  let Inst{31-30} = op;               // Top two bits are the 'op' field
+
+  // Bit attributes specific to SparcV8 instructions
+  bit isPasi       = 0; // Does this instruction affect an alternate addr space?
+  bit isPrivileged = 0; // Is this a privileged instruction?
 }
 
-// All of the SparcV8 instruction formats, plus a pseudo-instruction format:
+include "SparcV8Instrs_F2.td"
-def Pseudo : Format<0>;
+include "SparcV8Instrs_F3.td"
-def IForm : Format<1>;
-def BForm : Format<2>;
-def SCForm : Format<3>;
-def DForm : Format<4>;
-def XForm : Format<5>;
-def XLForm : Format<6>;
-def XFXForm : Format<7>;
-def XFLForm : Format<8>;
-def XOForm : Format<9>;
-def AForm : Format<10>;
-def MForm : Format<11>;
-
-class PPCInst<string nm, bits<6> opcd, Format f> : Instruction {
-  let Namespace = "SparcV8";
-
-  let Name = nm;
-  bits<6> Opcode = opcd;
-  Format Form = f;
-  bits<4> FormBits = Form.Value;
-}
-
-// Pseudo-instructions:
-def PHI : PPCInst<"PHI", 0, Pseudo>;          // PHI node...
-def NOP : PPCInst<"NOP", 0, Pseudo>;          // No-op
-def ADJCALLSTACKDOWN : PPCInst<"ADJCALLSTACKDOWN", 0, Pseudo>;
-def ADJCALLSTACKUP : PPCInst<"ADJCALLSTACKUP", 0, Pseudo>;
-
 

lib/Target/SparcV8/SparcV8.td

@@ -31,10 +31,7 @@ def SparcV8 : Target {
 
   // According to the Mach-O Runtime ABI, these regs are nonvolatile across
   // calls:
-  let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
+  let CalleeSavedRegisters = [];
-    R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
-    F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
-    F30, F31, CR2, CR3, CR4];
 
   // Pull in Instruction Info:
   let InstructionSet = SparcV8InstrInfo;

lib/Target/SparcV8/SparcV8Instrs.td

@@ -1,4 +1,4 @@
-//===- SparcV8InstrInfo.td - Describe the SparcV8 Instruction Set -*- C++ -*-=//
+//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
 // 
 //                     The LLVM Compiler Infrastructure
 //
@@ -7,40 +7,30 @@
 // 
 //===----------------------------------------------------------------------===//
 //
+// This file describes the SparcV8 instructions in TableGen format.
 //
 //===----------------------------------------------------------------------===//
 
-class Format<bits<4> val> {
+include "../Target.td"
-  bits<4> Value = val;
+include "SparcV8Reg.td"
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+class InstV8 : Instruction {          // SparcV8 instruction baseline
+  field bits<32> Inst;
+
+  let Namespace = "V8";
+
+  bits<2> op;
+  let Inst{31-30} = op;               // Top two bits are the 'op' field
+
+  // Bit attributes specific to SparcV8 instructions
+  bit isPasi       = 0; // Does this instruction affect an alternate addr space?
+  bit isPrivileged = 0; // Is this a privileged instruction?
 }
 
-// All of the SparcV8 instruction formats, plus a pseudo-instruction format:
+include "SparcV8Instrs_F2.td"
-def Pseudo : Format<0>;
+include "SparcV8Instrs_F3.td"
-def IForm : Format<1>;
-def BForm : Format<2>;
-def SCForm : Format<3>;
-def DForm : Format<4>;
-def XForm : Format<5>;
-def XLForm : Format<6>;
-def XFXForm : Format<7>;
-def XFLForm : Format<8>;
-def XOForm : Format<9>;
-def AForm : Format<10>;
-def MForm : Format<11>;
-
-class PPCInst<string nm, bits<6> opcd, Format f> : Instruction {
-  let Namespace = "SparcV8";
-
-  let Name = nm;
-  bits<6> Opcode = opcd;
-  Format Form = f;
-  bits<4> FormBits = Form.Value;
-}
-
-// Pseudo-instructions:
-def PHI : PPCInst<"PHI", 0, Pseudo>;          // PHI node...
-def NOP : PPCInst<"NOP", 0, Pseudo>;          // No-op
-def ADJCALLSTACKDOWN : PPCInst<"ADJCALLSTACKDOWN", 0, Pseudo>;
-def ADJCALLSTACKUP : PPCInst<"ADJCALLSTACKUP", 0, Pseudo>;
-