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Added ICC, FCC as uses of movcc instruction to generate correct code when -mattr=v9 is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124027 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Venkatraman Govindaraju
parent
0ef755d905
commit
e105a3901f
@ -694,48 +694,57 @@ let Defs = [FCC] in {
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let Predicates = [HasV9], Constraints = "$T = $dst" in {
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// Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
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// FIXME: Add instruction encodings for the JIT some day.
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def MOVICCrr
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: Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc),
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"mov$cc %icc, $F, $dst",
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[(set IntRegs:$dst,
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(SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>;
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def MOVICCri
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: Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc),
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"mov$cc %icc, $F, $dst",
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[(set IntRegs:$dst,
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(SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>;
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let Uses = [ICC] in {
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def MOVICCrr
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: Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc),
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"mov$cc %icc, $F, $dst",
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[(set IntRegs:$dst,
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(SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>;
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def MOVICCri
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: Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc),
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"mov$cc %icc, $F, $dst",
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[(set IntRegs:$dst,
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(SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>;
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}
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def MOVFCCrr
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: Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc),
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"mov$cc %fcc0, $F, $dst",
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[(set IntRegs:$dst,
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(SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>;
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def MOVFCCri
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: Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc),
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"mov$cc %fcc0, $F, $dst",
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[(set IntRegs:$dst,
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(SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>;
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let Uses = [FCC] in {
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def MOVFCCrr
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: Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc),
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"mov$cc %fcc0, $F, $dst",
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[(set IntRegs:$dst,
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(SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>;
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def MOVFCCri
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: Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc),
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"mov$cc %fcc0, $F, $dst",
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[(set IntRegs:$dst,
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(SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>;
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}
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def FMOVS_ICC
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: Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc),
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"fmovs$cc %icc, $F, $dst",
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[(set FPRegs:$dst,
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(SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>;
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def FMOVD_ICC
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: Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
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"fmovd$cc %icc, $F, $dst",
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[(set DFPRegs:$dst,
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(SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>;
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def FMOVS_FCC
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: Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc),
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"fmovs$cc %fcc0, $F, $dst",
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[(set FPRegs:$dst,
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(SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>;
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def FMOVD_FCC
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: Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
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"fmovd$cc %fcc0, $F, $dst",
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[(set DFPRegs:$dst,
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(SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>;
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let Uses = [ICC] in {
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def FMOVS_ICC
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: Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc),
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"fmovs$cc %icc, $F, $dst",
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[(set FPRegs:$dst,
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(SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>;
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def FMOVD_ICC
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: Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
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"fmovd$cc %icc, $F, $dst",
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[(set DFPRegs:$dst,
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(SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>;
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}
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let Uses = [FCC] in {
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def FMOVS_FCC
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: Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc),
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"fmovs$cc %fcc0, $F, $dst",
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[(set FPRegs:$dst,
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(SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>;
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def FMOVD_FCC
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: Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
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"fmovd$cc %fcc0, $F, $dst",
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[(set DFPRegs:$dst,
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(SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>;
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}
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}
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@ -1,11 +1,16 @@
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; RUN: llc -march=sparc <%s | FileCheck %s
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; RUN: llc -march=sparc <%s | FileCheck %s -check-prefix=V8
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; RUN: llc -march=sparc -mattr=v9 <%s | FileCheck %s -check-prefix=V9
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define i32 @test_addx(i64 %a, i64 %b, i64 %c) nounwind readnone noinline {
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entry:
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; CHECK: addcc
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; CHECK-NOT: subcc
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; CHECK: addx
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; V8: addcc
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; V8-NOT: subcc
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; V8: addx
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; V9: addcc
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; V9-NOT: subcc
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; V9: addx
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; V9: mov{{e|ne}} %icc
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%0 = add i64 %a, %b
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%1 = icmp ugt i64 %0, %c
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%2 = zext i1 %1 to i32
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@ -15,9 +20,13 @@ entry:
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define i32 @test_select_int_icc(i32 %a, i32 %b, i32 %c) nounwind readnone noinline {
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entry:
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; CHECK: test_select_int_icc
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; CHECK: subcc
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; CHECK: {{be|bne}}
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; V8: test_select_int_icc
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; V8: subcc
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; V8: {{be|bne}}
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; V9: test_select_int_icc
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; V9: subcc
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; V9-NOT: {{be|bne}}
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; V9: mov{{e|ne}} %icc
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%0 = icmp eq i32 %a, 0
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%1 = select i1 %0, i32 %b, i32 %c
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ret i32 %1
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@ -26,9 +35,13 @@ entry:
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define float @test_select_fp_icc(i32 %a, float %f1, float %f2) nounwind readnone noinline {
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entry:
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; CHECK: test_select_fp_icc
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; CHECK: subcc
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; CHECK: {{be|bne}}
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; V8: test_select_fp_icc
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; V8: subcc
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; V8: {{be|bne}}
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; V9: test_select_fp_icc
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; V9: subcc
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; V9-NOT: {{be|bne}}
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; V9: fmovs{{e|ne}} %icc
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%0 = icmp eq i32 %a, 0
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%1 = select i1 %0, float %f1, float %f2
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ret float %1
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@ -36,9 +49,13 @@ entry:
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define double @test_select_dfp_icc(i32 %a, double %f1, double %f2) nounwind readnone noinline {
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entry:
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; CHECK: test_select_dfp_icc
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; CHECK: subcc
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; CHECK: {{be|bne}}
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; V8: test_select_dfp_icc
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; V8: subcc
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; V8: {{be|bne}}
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; V9: test_select_dfp_icc
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; V9: subcc
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; V9=NOT: {{be|bne}}
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; V9: fmovd{{e|ne}} %icc
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%0 = icmp eq i32 %a, 0
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%1 = select i1 %0, double %f1, double %f2
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ret double %1
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@ -46,9 +63,13 @@ entry:
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define i32 @test_select_int_fcc(float %f, i32 %a, i32 %b) nounwind readnone noinline {
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entry:
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;CHECK: test_select_int_fcc
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;CHECK: fcmps
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;CHECK: {{fbe|fbne}}
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;V8: test_select_int_fcc
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;V8: fcmps
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;V8: {{fbe|fbne}}
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;V9: test_select_int_fcc
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;V9: fcmps
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;V9-NOT: {{fbe|fbne}}
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;V9: mov{{e|ne}} %fcc0
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%0 = fcmp une float %f, 0.000000e+00
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%a.b = select i1 %0, i32 %a, i32 %b
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ret i32 %a.b
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@ -57,9 +78,13 @@ entry:
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define float @test_select_fp_fcc(float %f, float %f1, float %f2) nounwind readnone noinline {
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entry:
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;CHECK: test_select_fp_fcc
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;CHECK: fcmps
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;CHECK: {{fbe|fbne}}
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;V8: test_select_fp_fcc
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;V8: fcmps
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;V8: {{fbe|fbne}}
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;V9: test_select_fp_fcc
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;V9: fcmps
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;V9-NOT: {{fbe|fbne}}
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;V9: fmovs{{e|ne}} %fcc0
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%0 = fcmp une float %f, 0.000000e+00
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%1 = select i1 %0, float %f1, float %f2
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ret float %1
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@ -67,9 +92,13 @@ entry:
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define double @test_select_dfp_fcc(double %f, double %f1, double %f2) nounwind readnone noinline {
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entry:
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;CHECK: test_select_dfp_fcc
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;CHECK: fcmpd
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;CHECK: {{fbne|fbe}}
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;V8: test_select_dfp_fcc
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;V8: fcmpd
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;V8: {{fbne|fbe}}
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;V9: test_select_dfp_fcc
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;V9: fcmpd
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;V9-NOT: {{fbne|fbe}}
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;V9: fmovd{{e|ne}} %fcc0
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%0 = fcmp une double %f, 0.000000e+00
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%1 = select i1 %0, double %f1, double %f2
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ret double %1
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