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[AArch64] Refactoring aarch64-ldst-opt. NCF.
Remove narrow load / store instructions from getMatchingPairOpcode(), and add getMatchingWideOpcode(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@259914 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -363,6 +363,33 @@ static unsigned getMatchingNonSExtOpcode(unsigned Opc,
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}
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}
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}
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}
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static unsigned getMatchingWideOpcode(unsigned Opc) {
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switch (Opc) {
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default:
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llvm_unreachable("Opcode has no wide equivalent!");
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case AArch64::STRBBui:
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return AArch64::STRHHui;
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case AArch64::STRHHui:
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return AArch64::STRWui;
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case AArch64::STURBBi:
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return AArch64::STURHHi;
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case AArch64::STURHHi:
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return AArch64::STURWi;
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case AArch64::LDRHHui:
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case AArch64::LDRSHWui:
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return AArch64::LDRWui;
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case AArch64::LDURHHi:
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case AArch64::LDURSHWi:
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return AArch64::LDURWi;
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case AArch64::LDRBBui:
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case AArch64::LDRSBWui:
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return AArch64::LDRHHui;
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case AArch64::LDURBBi:
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case AArch64::LDURSBWi:
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return AArch64::LDURHHi;
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}
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}
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static unsigned getMatchingPairOpcode(unsigned Opc) {
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static unsigned getMatchingPairOpcode(unsigned Opc) {
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switch (Opc) {
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switch (Opc) {
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default:
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default:
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@ -376,14 +403,6 @@ static unsigned getMatchingPairOpcode(unsigned Opc) {
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case AArch64::STRQui:
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case AArch64::STRQui:
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case AArch64::STURQi:
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case AArch64::STURQi:
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return AArch64::STPQi;
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return AArch64::STPQi;
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case AArch64::STRBBui:
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return AArch64::STRHHui;
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case AArch64::STRHHui:
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return AArch64::STRWui;
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case AArch64::STURBBi:
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return AArch64::STURHHi;
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case AArch64::STURHHi:
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return AArch64::STURWi;
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case AArch64::STRWui:
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case AArch64::STRWui:
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case AArch64::STURWi:
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case AArch64::STURWi:
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return AArch64::STPWi;
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return AArch64::STPWi;
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@ -408,18 +427,6 @@ static unsigned getMatchingPairOpcode(unsigned Opc) {
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case AArch64::LDRSWui:
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case AArch64::LDRSWui:
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case AArch64::LDURSWi:
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case AArch64::LDURSWi:
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return AArch64::LDPSWi;
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return AArch64::LDPSWi;
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case AArch64::LDRHHui:
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case AArch64::LDRSHWui:
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return AArch64::LDRWui;
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case AArch64::LDURHHi:
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case AArch64::LDURSHWi:
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return AArch64::LDURWi;
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case AArch64::LDRBBui:
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case AArch64::LDRSBWui:
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return AArch64::LDRHHui;
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case AArch64::LDURBBi:
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case AArch64::LDURSBWi:
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return AArch64::LDURHHi;
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}
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}
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}
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}
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@ -642,7 +649,6 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
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int OffsetStride = IsUnscaled ? getMemScale(I) : 1;
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int OffsetStride = IsUnscaled ? getMemScale(I) : 1;
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bool MergeForward = Flags.getMergeForward();
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bool MergeForward = Flags.getMergeForward();
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unsigned NewOpc = getMatchingPairOpcode(Opc);
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// Insert our new paired instruction after whichever of the paired
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// Insert our new paired instruction after whichever of the paired
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// instructions MergeForward indicates.
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// instructions MergeForward indicates.
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MachineBasicBlock::iterator InsertionPoint = MergeForward ? Paired : I;
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MachineBasicBlock::iterator InsertionPoint = MergeForward ? Paired : I;
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@ -683,7 +689,7 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
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// Construct the new load instruction.
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// Construct the new load instruction.
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MachineInstr *NewMemMI, *BitExtMI1, *BitExtMI2;
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MachineInstr *NewMemMI, *BitExtMI1, *BitExtMI2;
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NewMemMI = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
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NewMemMI = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
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TII->get(NewOpc))
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TII->get(getMatchingWideOpcode(Opc)))
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.addOperand(getLdStRegOp(RtNewDest))
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.addOperand(getLdStRegOp(RtNewDest))
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.addOperand(BaseRegOp)
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.addOperand(BaseRegOp)
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.addImm(OffsetImm)
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.addImm(OffsetImm)
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@ -775,7 +781,7 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
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OffsetImm /= 2;
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OffsetImm /= 2;
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}
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}
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MIB = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
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MIB = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
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TII->get(NewOpc))
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TII->get(getMatchingWideOpcode(Opc)))
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.addOperand(getLdStRegOp(I))
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.addOperand(getLdStRegOp(I))
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.addOperand(BaseRegOp)
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.addOperand(BaseRegOp)
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.addImm(OffsetImm)
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.addImm(OffsetImm)
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@ -785,7 +791,7 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
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if (IsUnscaled)
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if (IsUnscaled)
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OffsetImm /= OffsetStride;
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OffsetImm /= OffsetStride;
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MIB = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
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MIB = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
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TII->get(NewOpc))
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TII->get(getMatchingPairOpcode(Opc)))
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.addOperand(getLdStRegOp(RtMI))
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.addOperand(getLdStRegOp(RtMI))
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.addOperand(getLdStRegOp(Rt2MI))
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.addOperand(getLdStRegOp(Rt2MI))
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.addOperand(BaseRegOp)
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.addOperand(BaseRegOp)
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@ -1096,7 +1102,7 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
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if (FirstMI->modifiesRegister(BaseReg, TRI))
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if (FirstMI->modifiesRegister(BaseReg, TRI))
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return E;
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return E;
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// Early exit if the offset if not possible to match. (6 bits of positive
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// Early exit if the offset is not possible to match. (6 bits of positive
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// range, plus allow an extra one in case we find a later insn that matches
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// range, plus allow an extra one in case we find a later insn that matches
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// with Offset-1)
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// with Offset-1)
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int OffsetStride = IsUnscaled ? getMemScale(FirstMI) : 1;
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int OffsetStride = IsUnscaled ? getMemScale(FirstMI) : 1;
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@ -1580,6 +1586,13 @@ bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB,
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// ldr w0, [x2]
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// ldr w0, [x2]
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// ubfx w1, w0, #16, #16
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// ubfx w1, w0, #16, #16
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// and w0, w0, #ffff
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// and w0, w0, #ffff
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//
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// Also merge adjacent zero stores into a wider store.
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// e.g.,
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// strh wzr, [x0]
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// strh wzr, [x0, #2]
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// ; becomes
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// str wzr, [x0]
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for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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enableNarrowLdOpt && MBBI != E;) {
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enableNarrowLdOpt && MBBI != E;) {
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MachineInstr *MI = MBBI;
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MachineInstr *MI = MBBI;
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