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ARM64: start porting regression test suite from AArch64

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206166 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2014-04-14 12:50:41 +00:00
parent c81e5d6e64
commit e23fabc2ac
4 changed files with 31 additions and 22 deletions
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27
test/CodeGen/AArch64/128bit_load_store.ll
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@ -1,7 +1,8 @@
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=neon | FileCheck %s
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=neon| FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=neon | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64
define void @test_store_f128(fp128* %ptr, fp128 %val) #0 {
; CHECK: test_store_f128
; CHECK-LABEL: test_store_f128
; CHECK: str {{q[0-9]+}}, [{{x[0-9]+}}]
entry:
store fp128 %val, fp128* %ptr, align 16
@ -9,7 +10,7 @@ entry:
}
define fp128 @test_load_f128(fp128* readonly %ptr) #2 {
; CHECK: test_load_f128
; CHECK-LABEL: test_load_f128
; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}]
entry:
%0 = load fp128* %ptr, align 16
@ -17,9 +18,12 @@ entry:
}
define void @test_vstrq_p128(i128* %ptr, i128 %val) #0 {
; CHECK: test_vstrq_p128
; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, #8]
; CHECK-NEXT: str {{x[0-9]+}}, [{{x[0-9]+}}]
; CHECK-ARM64-LABEL: test_vstrq_p128
; CHECK-ARM64: stp {{x[0-9]+}}, {{x[0-9]+}}, [{{x[0-9]+}}]
; CHECK-AARCH64-LABEL: test_vstrq_p128
; CHECK-AARCH64: str {{x[0-9]+}}, [{{x[0-9]+}}, #8]
; CHECK-AARCH64: str {{x[0-9]+}}, [{{x[0-9]+}}]
entry:
%0 = bitcast i128* %ptr to fp128*
%1 = bitcast i128 %val to fp128
@ -28,9 +32,12 @@ entry:
}
define i128 @test_vldrq_p128(i128* readonly %ptr) #2 {
; CHECK: test_vldrq_p128
; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}]
; CHECK-NEXT: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #8]
; CHECK-ARM64-LABEL: test_vldrq_p128
; CHECK-ARM64: ldp {{x[0-9]+}}, {{x[0-9]+}}, [{{x[0-9]+}}]
; CHECK-AARCH64-LABEL: test_vldrq_p128
; CHECK-AARCH64: ldr {{x[0-9]+}}, [{{x[0-9]+}}]
; CHECK-AARCH64: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #8]
entry:
%0 = bitcast i128* %ptr to fp128*
%1 = load fp128* %0, align 16
@ -39,7 +46,7 @@ entry:
}
define void @test_ld_st_p128(i128* nocapture %ptr) #0 {
; CHECK: test_ld_st_p128
; CHECK-LABEL: test_ld_st_p128
; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}]
; CHECK-NEXT: str {{q[0-9]+}}, [{{x[0-9]+}}, #16]
entry:

1
test/CodeGen/AArch64/adc.ll
View File

@ -1,5 +1,6 @@
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck --check-prefix=CHECK --check-prefix=CHECK-LE %s
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64_be-none-linux-gnu | FileCheck --check-prefix=CHECK --check-prefix=CHECK-BE %s
; RUN: llc -verify-machineinstrs < %s -mtriple=arm64 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-LE %s
define i128 @test_simple(i128 %a, i128 %b, i128 %c) {
; CHECK-LABEL: test_simple:

23
test/CodeGen/AArch64/addsub.ll
View File

@ -1,4 +1,5 @@
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-linux-gnu | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -march=arm64 | FileCheck %s
; Note that this should be refactored (for efficiency if nothing else)
; when the PCS is implemented so we don't have to worry about the
@ -28,12 +29,12 @@ define void @add_small() {
define void @add_med() {
; CHECK-LABEL: add_med:
; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #3567, lsl #12
; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{#3567, lsl #12|#14610432}}
%val32 = load i32* @var_i32
%newval32 = add i32 %val32, 14610432 ; =0xdef000
store i32 %newval32, i32* @var_i32
; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #4095, lsl #12
; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{#4095, lsl #12|#16773120}}
%val64 = load i64* @var_i64
%newval64 = add i64 %val64, 16773120 ; =0xfff000
store i64 %newval64, i64* @var_i64
@ -62,12 +63,12 @@ define void @sub_small() {
define void @sub_med() {
; CHECK-LABEL: sub_med:
; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #3567, lsl #12
; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{#3567, lsl #12|#14610432}}
%val32 = load i32* @var_i32
%newval32 = sub i32 %val32, 14610432 ; =0xdef000
store i32 %newval32, i32* @var_i32
; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, #4095, lsl #12
; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{#4095, lsl #12|#16773120}}
%val64 = load i64* @var_i64
%newval64 = sub i64 %val64, 16773120 ; =0xfff000
store i64 %newval64, i64* @var_i64
@ -80,13 +81,13 @@ define void @testing() {
%val = load i32* @var_i32
; CHECK: cmp {{w[0-9]+}}, #4095
; CHECK: b.ne .LBB4_6
; CHECK: b.ne [[RET:.?LBB[0-9]+_[0-9]+]]
%cmp_pos_small = icmp ne i32 %val, 4095
br i1 %cmp_pos_small, label %ret, label %test2
test2:
; CHECK: cmp {{w[0-9]+}}, #3567, lsl #12
; CHECK: b.lo .LBB4_6
; CHECK: cmp {{w[0-9]+}}, {{#3567, lsl #12|#14610432}}
; CHECK: b.{{cc|lo}} [[RET]]
%newval2 = add i32 %val, 1
store i32 %newval2, i32* @var_i32
%cmp_pos_big = icmp ult i32 %val, 14610432
@ -94,7 +95,7 @@ test2:
test3:
; CHECK: cmp {{w[0-9]+}}, #123
; CHECK: b.lt .LBB4_6
; CHECK: b.lt [[RET]]
%newval3 = add i32 %val, 2
store i32 %newval3, i32* @var_i32
%cmp_pos_slt = icmp slt i32 %val, 123
@ -102,7 +103,7 @@ test3:
test4:
; CHECK: cmp {{w[0-9]+}}, #321
; CHECK: b.gt .LBB4_6
; CHECK: b.gt [[RET]]
%newval4 = add i32 %val, 3
store i32 %newval4, i32* @var_i32
%cmp_pos_sgt = icmp sgt i32 %val, 321
@ -110,7 +111,7 @@ test4:
test5:
; CHECK: cmn {{w[0-9]+}}, #444
; CHECK: b.gt .LBB4_6
; CHECK: b.gt [[RET]]
%newval5 = add i32 %val, 4
store i32 %newval5, i32* @var_i32
%cmp_neg_uge = icmp sgt i32 %val, -444

2
test/CodeGen/AArch64/lit.local.cfg
View File

@ -1,4 +1,4 @@
targets = set(config.root.targets_to_build.split())
if not 'AArch64' in targets:
if 'AArch64' not in targets or 'ARM64' not in targets:
config.unsupported = True