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[TableGen] Replace instructions() with getInstructionsByEnumValue(). No need to make an iterator_range when we already have a function that returns an ArrayRef. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@258019 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1400,7 +1400,7 @@ void AsmMatcherInfo::buildInfo() {
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AsmVariant->getValueAsString("BreakCharacters");
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Variant.AsmVariantNo = AsmVariant->getValueAsInt("Variant");
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for (const CodeGenInstruction *CGI : Target.instructions()) {
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for (const CodeGenInstruction *CGI : Target.getInstructionsByEnumValue()) {
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// If the tblgen -match-prefix option is specified (for tblgen hackers),
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// filter the set of instructions we consider.
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@ -68,7 +68,7 @@ struct InstRegexOp : public SetTheory::Operator {
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}
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RegexList.push_back(Regex(pat));
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}
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for (const CodeGenInstruction *Inst : Target.instructions()) {
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for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
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for (auto &R : RegexList) {
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if (R.match(Inst->TheDef->getName()))
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Elts.insert(Inst->TheDef);
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@ -204,7 +204,7 @@ void CodeGenSchedModels::collectSchedRW() {
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// Find all SchedReadWrites referenced by instruction defs.
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RecVec SWDefs, SRDefs;
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for (const CodeGenInstruction *Inst : Target.instructions()) {
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for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
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Record *SchedDef = Inst->TheDef;
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if (SchedDef->isValueUnset("SchedRW"))
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continue;
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@ -498,7 +498,7 @@ void CodeGenSchedModels::collectSchedClasses() {
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// Create a SchedClass for each unique combination of itinerary class and
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// SchedRW list.
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for (const CodeGenInstruction *Inst : Target.instructions()) {
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for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
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Record *ItinDef = Inst->TheDef->getValueAsDef("Itinerary");
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IdxVec Writes, Reads;
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if (!Inst->TheDef->isValueUnset("SchedRW"))
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@ -523,7 +523,7 @@ void CodeGenSchedModels::collectSchedClasses() {
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if (!EnableDump)
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return;
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for (const CodeGenInstruction *Inst : Target.instructions()) {
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for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
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std::string InstName = Inst->TheDef->getName();
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unsigned SCIdx = InstrClassMap.lookup(Inst->TheDef);
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if (!SCIdx) {
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@ -162,7 +162,7 @@ const std::string &CodeGenTarget::getName() const {
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}
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std::string CodeGenTarget::getInstNamespace() const {
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for (const CodeGenInstruction *Inst : instructions()) {
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for (const CodeGenInstruction *Inst : getInstructionsByEnumValue()) {
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// Make sure not to pick up "TargetOpcode" by accidentally getting
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// the namespace off the PHI instruction or something.
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if (Inst->Namespace != "TargetOpcode")
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@ -170,9 +170,6 @@ public:
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typedef ArrayRef<const CodeGenInstruction *>::const_iterator inst_iterator;
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inst_iterator inst_begin() const{return getInstructionsByEnumValue().begin();}
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inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); }
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iterator_range<inst_iterator> instructions() const {
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return make_range(inst_begin(), inst_end());
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}
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/// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]?
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@ -177,7 +177,7 @@ void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
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OS << "\n";
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const CodeGenTarget &Target = CDP.getTargetInfo();
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for (const CodeGenInstruction *Inst : Target.instructions()) {
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for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
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std::vector<std::string> OperandInfo = GetOperandInfo(*Inst);
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unsigned &N = OperandInfoIDs[OperandInfo];
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if (N != 0) continue;
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@ -358,7 +358,7 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
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unsigned ListNumber = 0;
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// Emit all of the instruction's implicit uses and defs.
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for (const CodeGenInstruction *II : Target.instructions()) {
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for (const CodeGenInstruction *II : Target.getInstructionsByEnumValue()) {
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Record *Inst = II->TheDef;
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std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
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if (!Uses.empty()) {
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