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Don't charge the full latency for anti and output dependencies. This is

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an area where eventually it would be good to use target-dependent
information.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60498 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-12-03 19:37:34 +00:00
parent f94a327361
commit e561751e98
1 changed files with 6 additions and 3 deletions
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9
lib/CodeGen/PostRASchedulerList.cpp
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@ -160,9 +160,12 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
for (SUnit::pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
P != PE; ++P) {
SUnit *PredSU = P->Dep;
unsigned PredLatency = PredSU->CycleBound + PredSU->Latency;
if (SU->CycleBound < PredLatency) {
SU->CycleBound = PredLatency;
// This assumes that there's no delay for reusing registers.
unsigned PredLatency = (P->isCtrl && P->Reg != 0) ? 1 : PredSU->Latency;
unsigned PredTotalLatency = PredSU->CycleBound + PredLatency;
if (SU->CycleBound < PredTotalLatency ||
(SU->CycleBound == PredTotalLatency && !P->isAntiDep)) {
SU->CycleBound = PredTotalLatency;
CriticalPath[*I] = &*P;
}
}