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* Elimiante a bunch of functions from InstrSelectionSupport.h, replacing users

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of them with BUildMI calls instead.
* Fix def information in instructions generated by prologepilog inserter


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5287 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2003-01-15 00:03:28 +00:00
parent ed4fb8f3ec
commit e5b1ed9db9
3 changed files with 62 additions and 65 deletions
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59
lib/Target/SparcV9/SparcV9InstrInfo.cpp
View File

@ -9,6 +9,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionInfo.h"
#include "llvm/CodeGen/MachineCodeForInstruction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Function.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
@ -63,7 +64,7 @@ CreateSETUWConst(const TargetMachine& target, uint32_t C,
{
if (miSETHI)
{ // unsigned value with high-order bits set using SETHI
miOR = Create3OperandInstr_UImmed(OR, dest, C, dest);
miOR = BuildMI(OR, 3).addReg(dest).addZImm(C).addReg(dest, MOTy::Def);
miOR->setOperandLo32(1);
}
else
@ -97,17 +98,13 @@ static inline void
CreateSETSWConst(const TargetMachine& target, int32_t C,
Instruction* dest, vector<MachineInstr*>& mvec)
{
MachineInstr* MI;
// Set the low 32 bits of dest
CreateSETUWConst(target, (uint32_t) C, dest, mvec, /*isSigned*/true);
// Sign-extend to the high 32 bits if needed
if (C < 0 && (-C) > (int32_t) MAXSIMM)
{
MI = Create3OperandInstr_UImmed(SRA, dest, 0, dest);
mvec.push_back(MI);
}
mvec.push_back(BuildMI(SRA, 3).addReg(dest).addZImm(0).addReg(dest,
MOTy::Def));
}
@ -134,15 +131,15 @@ CreateSETXConst(const TargetMachine& target, uint64_t C,
CreateSETUWConst(target, (C >> 32), tmpReg, mvec);
// Shift tmpReg left by 32 bits
MI = Create3OperandInstr_UImmed(SLLX, tmpReg, 32, tmpReg);
mvec.push_back(MI);
mvec.push_back(BuildMI(SLLX, 3).addReg(tmpReg).addZImm(32).addReg(tmpReg,
MOTy::Def));
// Code to set the low 32 bits of the value in register `dest'
CreateSETUWConst(target, C, dest, mvec);
// dest = OR(tmpReg, dest)
MI = Create3OperandInstr(OR, dest, tmpReg, dest);
mvec.push_back(MI);
mvec.push_back(BuildMI(OR, 3).addReg(dest).addReg(tmpReg).addReg(dest,
MOTy::Def));
}
@ -164,7 +161,7 @@ CreateSETUWLabel(const TargetMachine& target, Value* val,
mvec.push_back(MI);
// Set the low 10 bits in dest
MI = Create3OperandInstr(OR, dest, val, dest);
MI = BuildMI(OR, 3).addReg(dest).addReg(val).addReg(dest, MOTy::Def);
MI->setOperandLo32(1);
mvec.push_back(MI);
}
@ -190,21 +187,20 @@ CreateSETXLabel(const TargetMachine& target,
MI->setOperandHi64(0);
mvec.push_back(MI);
MI = Create3OperandInstr_Addr(OR, tmpReg, val, tmpReg);
MI = BuildMI(OR, 3).addReg(tmpReg).addPCDisp(val).addReg(tmpReg, MOTy::Def);
MI->setOperandLo64(1);
mvec.push_back(MI);
MI = Create3OperandInstr_UImmed(SLLX, tmpReg, 32, tmpReg);
mvec.push_back(MI);
mvec.push_back(BuildMI(SLLX, 3).addReg(tmpReg).addZImm(32).addReg(tmpReg,
MOTy::Def));
MI = Create2OperandInstr_Addr(SETHI, val, dest);
MI->setOperandHi32(0);
mvec.push_back(MI);
MI = Create3OperandInstr(OR, dest, tmpReg, dest);
MI = BuildMI(OR, 3).addReg(dest).addReg(tmpReg).addReg(dest, MOTy::Def);
mvec.push_back(MI);
MI = Create3OperandInstr_Addr(OR, dest, val, dest);
MI = BuildMI(OR, 3).addReg(dest).addPCDisp(val).addReg(dest, MOTy::Def);
MI->setOperandLo32(1);
mvec.push_back(MI);
}
@ -456,10 +452,9 @@ UltraSparcInstrInfo::CreateCodeToLoadConst(const TargetMachine& target,
// Generate the load instruction
int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0
MachineInstr* MI =
Create3OperandInstr_SImmed(ChooseLoadInstruction(val->getType()),
addrReg, zeroOffset, dest);
mvec.push_back(MI);
unsigned Opcode = ChooseLoadInstruction(val->getType());
mvec.push_back(BuildMI(Opcode, 3).addReg(addrReg).
addSImm(zeroOffset).addReg(dest, MOTy::Def));
// Make sure constant is emitted to constant pool in assembly code.
MachineFunction::get(F).getInfo()->addToConstantPool(cast<Constant>(val));
@ -630,12 +625,11 @@ UltraSparcInstrInfo::CreateCopyInstructionsByType(const TargetMachine& target,
// Make `src' the second operand, in case it is a constant
// Use (unsigned long) 0 for a NULL pointer value.
//
const Type* zeroValueType =
isa<PointerType>(resultType) ? Type::ULongTy : resultType;
MachineInstr* minstr =
Create3OperandInstr(opCode, Constant::getNullValue(zeroValueType),
src, dest);
mvec.push_back(minstr);
const Type* Ty =isa<PointerType>(resultType) ? Type::ULongTy : resultType;
MachineInstr* MI =
BuildMI(opCode, 3).addReg(Constant::getNullValue(Ty))
.addReg(src).addReg(dest, MOTy::Def);
mvec.push_back(MI);
}
}
@ -661,14 +655,13 @@ CreateBitExtensionInstructions(bool signExtend,
TmpInstruction *tmpI = new TmpInstruction(destVal->getType(),
srcVal, destVal, "make32");
mcfi.addTemp(tmpI);
M = Create3OperandInstr_UImmed(SLLX, srcVal, 32-numLowBits, tmpI);
mvec.push_back(M);
mvec.push_back(BuildMI(SLLX, 3).addReg(srcVal).addZImm(32-numLowBits)
.addReg(tmpI, MOTy::Def));
srcVal = tmpI;
}
M = Create3OperandInstr_UImmed(signExtend? SRA : SRL,
srcVal, 32-numLowBits, destVal);
mvec.push_back(M);
mvec.push_back(BuildMI(signExtend? SRA : SRL, 3).addReg(srcVal)
.addZImm(32-numLowBits).addReg(destVal, MOTy::Def));
}

55
lib/Target/SparcV9/SparcV9InstrSelection.cpp
View File

@ -8,7 +8,7 @@
#include "SparcInstrSelectionSupport.h"
#include "SparcRegClassInfo.h"
#include "llvm/CodeGen/InstrSelectionSupport.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineInstrAnnot.h"
#include "llvm/CodeGen/InstrForest.h"
#include "llvm/CodeGen/InstrSelection.h"
@ -546,8 +546,10 @@ CreateShiftInstructions(const TargetMachine& target,
}
MachineInstr* M = (optArgVal2 != NULL)
? Create3OperandInstr(shiftOpCode, argVal1, optArgVal2, shiftDest)
: Create3OperandInstr_UImmed(shiftOpCode, argVal1, optShiftNum, shiftDest);
? BuildMI(shiftOpCode, 3).addReg(argVal1).addReg(optArgVal2)
.addReg(shiftDest, MOTy::Def)
: BuildMI(shiftOpCode, 3).addReg(argVal1).addZImm(optShiftNum)
.addReg(shiftDest, MOTy::Def);
mvec.push_back(M);
if (shiftDest != destVal)
@ -601,14 +603,10 @@ CreateMulConstInstruction(const TargetMachine &target, Function* F,
if (C == 0 || C == 1)
{
cost = target.getInstrInfo().minLatency(ADD);
unsigned ZeroReg = target.getRegInfo().getZeroRegNum();
MachineInstr* M = (C == 0)
? Create3OperandInstr_Reg(ADD,
target.getRegInfo().getZeroRegNum(),
target.getRegInfo().getZeroRegNum(),
destVal)
: Create3OperandInstr_Reg(ADD, lval,
target.getRegInfo().getZeroRegNum(),
destVal);
? Create3OperandInstr_Reg(ADD, ZeroReg, ZeroReg, destVal)
: Create3OperandInstr_Reg(ADD, lval, ZeroReg, destVal);
mvec.push_back(M);
}
else if (isPowerOf2(C, pow))
@ -1728,10 +1726,11 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,quot);
mvec.push_back(M);
M = Create3OperandInstr(ChooseMulInstructionByType(
subtreeRoot->getInstruction()->getType()),
quot, subtreeRoot->rightChild()->getValue(),
prod);
unsigned MulOpcode =
ChooseMulInstructionByType(subtreeRoot->getInstruction()->getType());
Value *MulRHS = subtreeRoot->rightChild()->getValue();
M = BuildMI(MulOpcode, 3).addReg(quot).addReg(MulRHS).addReg(prod,
MOTy::Def);
mvec.push_back(M);
M = new MachineInstr(ChooseSubInstructionByType(
@ -1759,9 +1758,10 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
Value* notArg = BinaryOperator::getNotArgument(
cast<BinaryOperator>(notNode->getInstruction()));
notNode->markFoldedIntoParent();
mvec.push_back(Create3OperandInstr(ANDN,
subtreeRoot->leftChild()->getValue(),
notArg, subtreeRoot->getValue()));
Value *LHS = subtreeRoot->leftChild()->getValue();
Value *Dest = subtreeRoot->getValue();
mvec.push_back(BuildMI(ANDN, 3).addReg(LHS).addReg(notArg)
.addReg(Dest, MOTy::Def));
break;
}
@ -1781,9 +1781,10 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
Value* notArg = BinaryOperator::getNotArgument(
cast<BinaryOperator>(notNode->getInstruction()));
notNode->markFoldedIntoParent();
mvec.push_back(Create3OperandInstr(ORN,
subtreeRoot->leftChild()->getValue(),
notArg, subtreeRoot->getValue()));
Value *LHS = subtreeRoot->leftChild()->getValue();
Value *Dest = subtreeRoot->getValue();
mvec.push_back(BuildMI(ORN, 3).addReg(LHS).addReg(notArg)
.addReg(Dest, MOTy::Def));
break;
}
@ -1803,9 +1804,10 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
Value* notArg = BinaryOperator::getNotArgument(
cast<BinaryOperator>(notNode->getInstruction()));
notNode->markFoldedIntoParent();
mvec.push_back(Create3OperandInstr(XNOR,
subtreeRoot->leftChild()->getValue(),
notArg, subtreeRoot->getValue()));
Value *LHS = subtreeRoot->leftChild()->getValue();
Value *Dest = subtreeRoot->getValue();
mvec.push_back(BuildMI(XNOR, 3).addReg(LHS).addReg(notArg)
.addReg(Dest, MOTy::Def));
break;
}
@ -2010,8 +2012,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
if (isa<Function>(callee)) // direct function call
M = Create1OperandInstr_Addr(CALL, callee);
else // indirect function call
M = Create3OperandInstr_SImmed(JMPLCALL, callee,
(int64_t) 0, retAddrReg);
M = BuildMI(JMPLCALL,
3).addReg(callee).addSImm((int64_t)0).addReg(retAddrReg);
mvec.push_back(M);
const FunctionType* funcType =
@ -2172,7 +2174,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
for (unsigned i=0, N=mvec.size(); i < N; ++i)
mvec[i]->substituteValue(dest, tmpI);
M = Create3OperandInstr_UImmed(SRL, tmpI, 8*(4-destSize), dest);
M = BuildMI(SRL, 3).addReg(tmpI).addZImm(8*(4-destSize))
.addReg(dest, MOTy::Def);
mvec.push_back(M);
}
else if (destSize < target.getTargetData().getIntegerRegize())

13
lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
View File

@ -63,7 +63,8 @@ void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF)
int32_t C = - (int) staticStackSize;
int SP = TM.getRegInfo().getStackPointer();
if (TM.getInstrInfo().constantFitsInImmedField(SAVE, staticStackSize)) {
mvec.push_back(BuildMI(SAVE, 3).addMReg(SP).addSImm(C).addMReg(SP));
mvec.push_back(BuildMI(SAVE, 3).addMReg(SP).addSImm(C).addMReg(SP,
MOTy::Def));
} else {
// We have to put the stack size value into a register before SAVE.
// Use register %g1 since it is volatile across calls. Note that the
@ -74,19 +75,19 @@ void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF)
TM.getRegInfo().getRegClassIDOfType(Type::IntTy),
SparcIntRegClass::g1);
MachineInstr* M = BuildMI(SETHI, 2).addSImm(C).addMReg(uregNum);
MachineInstr* M = BuildMI(SETHI, 2).addSImm(C).addMReg(uregNum, MOTy::Def);
M->setOperandHi32(0);
mvec.push_back(M);
M = BuildMI(OR, 3).addMReg(uregNum).addSImm(C).addMReg(uregNum);
M = BuildMI(OR, 3).addMReg(uregNum).addSImm(C).addMReg(uregNum, MOTy::Def);
M->setOperandLo32(1);
mvec.push_back(M);
M = BuildMI(SRA, 3).addMReg(uregNum).addZImm(0).addMReg(uregNum);
M = BuildMI(SRA, 3).addMReg(uregNum).addZImm(0).addMReg(uregNum, MOTy::Def);
mvec.push_back(M);
// Now generate the SAVE using the value in register %g1
M = BuildMI(SAVE, 3).addMReg(SP).addMReg(uregNum).addMReg(SP);
M = BuildMI(SAVE, 3).addMReg(SP).addMReg(uregNum).addMReg(SP, MOTy::Def);
mvec.push_back(M);
}
@ -106,7 +107,7 @@ void InsertPrologEpilogCode::InsertEpilogCode(MachineFunction &MF)
{
int ZR = TM.getRegInfo().getZeroRegNum();
MachineInstr *Restore =
BuildMI(RESTORE, 3).addMReg(ZR).addSImm(0).addMReg(ZR);
BuildMI(RESTORE, 3).addMReg(ZR).addSImm(0).addMReg(ZR, MOTy::Def);
MachineCodeForInstruction &termMvec =
MachineCodeForInstruction::get(TermInst);