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Revert "[mips][mt][6/7] Add support for mftr, mttr instructions."
This reverts r307836, it broke one of the buildbots. Reverting while I investigate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307939 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Dardis
parent
92aa19c981
commit
e603cb062f
@ -304,9 +304,6 @@ class MipsAsmParser : public MCTargetAsmParser {
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bool expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI);
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bool expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI);
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bool reportParseError(Twine ErrorMsg);
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bool reportParseError(SMLoc Loc, Twine ErrorMsg);
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@ -2514,16 +2511,6 @@ MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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return expandSeq(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
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case Mips::SEQIMacro:
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return expandSeqI(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
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case Mips::MFTC0: case Mips::MTTC0:
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case Mips::MFTGPR: case Mips::MTTGPR:
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case Mips::MFTLO: case Mips::MTTLO:
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case Mips::MFTHI: case Mips::MTTHI:
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case Mips::MFTACX: case Mips::MTTACX:
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case Mips::MFTDSP: case Mips::MTTDSP:
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case Mips::MFTC1: case Mips::MTTC1:
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case Mips::MFTHC1: case Mips::MTTHC1:
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case Mips::CFTC1: case Mips::CTTC1:
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return expandMXTRAlias(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
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}
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}
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@ -4895,212 +4882,6 @@ bool MipsAsmParser::expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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return false;
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}
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// Map the DSP accumulator and control register to the corresponding gpr
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// operand. Unlike the other alias, the m(f|t)t(lo|hi|acx) instructions
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// do not map the DSP registers contigously to gpr registers.
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static unsigned getRegisterForMxtrDSP(MCInst &Inst, bool IsMFDSP) {
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switch (Inst.getOpcode()) {
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case Mips::MFTLO:
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case Mips::MTTLO:
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switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) {
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case Mips::AC0:
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return Mips::ZERO;
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case Mips::AC1:
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return Mips::A0;
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case Mips::AC2:
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return Mips::T0;
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case Mips::AC3:
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return Mips::T4;
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default:
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llvm_unreachable("Unknown register for 'mttr' alias!");
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}
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case Mips::MFTHI:
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case Mips::MTTHI:
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switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) {
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case Mips::AC0:
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return Mips::AT;
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case Mips::AC1:
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return Mips::A1;
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case Mips::AC2:
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return Mips::T1;
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case Mips::AC3:
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return Mips::T5;
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default:
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llvm_unreachable("Unknown register for 'mttr' alias!");
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}
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case Mips::MFTACX:
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case Mips::MTTACX:
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switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) {
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case Mips::AC0:
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return Mips::V0;
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case Mips::AC1:
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return Mips::A2;
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case Mips::AC2:
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return Mips::T2;
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case Mips::AC3:
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return Mips::T6;
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default:
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llvm_unreachable("Unknown register for 'mttr' alias!");
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}
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case Mips::MFTDSP:
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case Mips::MTTDSP:
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return Mips::S0;
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default:
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llvm_unreachable("Unknown instruction for 'mttr' dsp alias!");
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}
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}
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// Map the floating point register operand to the corresponding register
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// operand.
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static unsigned getRegisterForMxtrFP(MCInst &Inst, bool IsMFTC1) {
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switch (Inst.getOperand(IsMFTC1 ? 1 : 0).getReg()) {
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case Mips::F0: return Mips::ZERO;
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case Mips::F1: return Mips::AT;
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case Mips::F2: return Mips::V0;
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case Mips::F3: return Mips::V1;
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case Mips::F4: return Mips::A0;
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case Mips::F5: return Mips::A1;
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case Mips::F6: return Mips::A2;
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case Mips::F7: return Mips::A3;
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case Mips::F8: return Mips::T0;
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case Mips::F9: return Mips::T1;
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case Mips::F10: return Mips::T2;
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case Mips::F11: return Mips::T3;
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case Mips::F12: return Mips::T4;
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case Mips::F13: return Mips::T5;
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case Mips::F14: return Mips::T6;
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case Mips::F15: return Mips::T7;
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case Mips::F16: return Mips::S0;
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case Mips::F17: return Mips::S1;
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case Mips::F18: return Mips::S2;
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case Mips::F19: return Mips::S3;
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case Mips::F20: return Mips::S4;
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case Mips::F21: return Mips::S5;
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case Mips::F22: return Mips::S6;
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case Mips::F23: return Mips::S7;
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case Mips::F24: return Mips::T8;
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case Mips::F25: return Mips::T9;
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case Mips::F26: return Mips::K0;
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case Mips::F27: return Mips::K1;
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case Mips::F28: return Mips::GP;
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case Mips::F29: return Mips::SP;
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case Mips::F30: return Mips::FP;
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case Mips::F31: return Mips::RA;
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default: llvm_unreachable("Unknown register for mttc1 alias!");
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}
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}
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// Map the coprocessor operand the corresponding gpr register operand.
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static unsigned getRegisterForMxtrC0(MCInst &Inst, bool IsMFTC0) {
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switch (Inst.getOperand(IsMFTC0 ? 1 : 0).getReg()) {
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case Mips::COP00: return Mips::ZERO;
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case Mips::COP01: return Mips::AT;
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case Mips::COP02: return Mips::V0;
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case Mips::COP03: return Mips::V1;
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case Mips::COP04: return Mips::A0;
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case Mips::COP05: return Mips::A1;
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case Mips::COP06: return Mips::A2;
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case Mips::COP07: return Mips::A3;
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case Mips::COP08: return Mips::T0;
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case Mips::COP09: return Mips::T1;
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case Mips::COP010: return Mips::T2;
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case Mips::COP011: return Mips::T3;
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case Mips::COP012: return Mips::T4;
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case Mips::COP013: return Mips::T5;
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case Mips::COP014: return Mips::T6;
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case Mips::COP015: return Mips::T7;
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case Mips::COP016: return Mips::S0;
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case Mips::COP017: return Mips::S1;
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case Mips::COP018: return Mips::S2;
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case Mips::COP019: return Mips::S3;
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case Mips::COP020: return Mips::S4;
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case Mips::COP021: return Mips::S5;
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case Mips::COP022: return Mips::S6;
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case Mips::COP023: return Mips::S7;
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case Mips::COP024: return Mips::T8;
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case Mips::COP025: return Mips::T9;
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case Mips::COP026: return Mips::K0;
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case Mips::COP027: return Mips::K1;
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case Mips::COP028: return Mips::GP;
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case Mips::COP029: return Mips::SP;
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case Mips::COP030: return Mips::FP;
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case Mips::COP031: return Mips::RA;
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default: llvm_unreachable("Unknown register for mttc0 alias!");
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}
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}
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/// Expand an alias of 'mftr' or 'mttr' into the full instruction, by producing
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/// an mftr or mttr with the correctly mapped gpr register, u, sel and h bits.
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bool MipsAsmParser::expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI) {
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MipsTargetStreamer &TOut = getTargetStreamer();
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unsigned rd = 0;
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unsigned u = 1;
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unsigned sel = 0;
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unsigned h = 0;
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bool IsMFTR = false;
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switch (Inst.getOpcode()) {
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case Mips::MFTC0:
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IsMFTR = true;
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LLVM_FALLTHROUGH;
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case Mips::MTTC0:
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u = 0;
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rd = getRegisterForMxtrC0(Inst, IsMFTR);
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sel = Inst.getOperand(2).getImm();
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break;
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case Mips::MFTGPR:
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IsMFTR = true;
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LLVM_FALLTHROUGH;
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case Mips::MTTGPR:
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rd = Inst.getOperand(IsMFTR ? 1 : 0).getReg();
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break;
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case Mips::MFTLO:
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case Mips::MFTHI:
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case Mips::MFTACX:
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case Mips::MFTDSP:
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IsMFTR = true;
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LLVM_FALLTHROUGH;
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case Mips::MTTLO:
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case Mips::MTTHI:
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case Mips::MTTACX:
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case Mips::MTTDSP:
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rd = getRegisterForMxtrDSP(Inst, IsMFTR);
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sel = 1;
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break;
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case Mips::MFTHC1:
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h = 1;
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LLVM_FALLTHROUGH;
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case Mips::MFTC1:
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IsMFTR = true;
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rd = getRegisterForMxtrFP(Inst, IsMFTR);
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sel = 2;
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break;
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case Mips::MTTHC1:
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h = 1;
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LLVM_FALLTHROUGH;
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case Mips::MTTC1:
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rd = getRegisterForMxtrFP(Inst, IsMFTR);
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sel = 2;
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break;
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case Mips::CFTC1:
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IsMFTR = true;
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LLVM_FALLTHROUGH;
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case Mips::CTTC1:
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rd = getRegisterForMxtrFP(Inst, IsMFTR);
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sel = 3;
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break;
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}
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unsigned Op0 = IsMFTR ? Inst.getOperand(0).getReg() : rd;
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unsigned Op1 =
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IsMFTR ? rd
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: (Inst.getOpcode() != Mips::MTTDSP ? Inst.getOperand(1).getReg()
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: Inst.getOperand(0).getReg());
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TOut.emitRRIII(IsMFTR ? Mips::MFTR : Mips::MTTR, Op0, Op1, u, sel, h, IDLoc,
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STI);
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return false;
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}
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unsigned
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MipsAsmParser::checkEarlyTargetMatchPredicate(MCInst &Inst,
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const OperandVector &Operands) {
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@ -193,21 +193,6 @@ void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1,
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emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI);
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}
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void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0,
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unsigned Reg1, int16_t Imm0, int16_t Imm1,
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int16_t Imm2, SMLoc IDLoc,
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const MCSubtargetInfo *STI) {
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MCInst TmpInst;
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TmpInst.setOpcode(Opcode);
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TmpInst.addOperand(MCOperand::createReg(Reg0));
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TmpInst.addOperand(MCOperand::createReg(Reg1));
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TmpInst.addOperand(MCOperand::createImm(Imm0));
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TmpInst.addOperand(MCOperand::createImm(Imm1));
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TmpInst.addOperand(MCOperand::createImm(Imm2));
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TmpInst.setLoc(IDLoc);
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getStreamer().EmitInstruction(TmpInst, *STI);
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}
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void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg,
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unsigned TrgReg, bool Is64Bit,
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const MCSubtargetInfo *STI) {
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@ -35,8 +35,6 @@ class FIELD5<bits<5> Val> {
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def FIELD5_1_DMT_EMT : FIELD5<0b00001>;
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def FIELD5_2_DMT_EMT : FIELD5<0b01111>;
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def FIELD5_1_2_DVPE_EVPE : FIELD5<0b00000>;
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def FIELD5_MFTR : FIELD5<0b01000>;
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def FIELD5_MTTR : FIELD5<0b01100>;
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class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
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bits<32> Inst;
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@ -52,25 +50,6 @@ class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
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let Inst{2-0} = 0b001;
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}
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class COP0_MFTTR_MT<FIELD5 Op> : MipsMTInst {
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bits<32> Inst;
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bits<5> rt;
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bits<5> rd;
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bits<1> u;
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bits<1> h;
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bits<3> sel;
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let Inst{31-26} = 0b010000; // COP0
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let Inst{25-21} = Op.Value; // MFMC0
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = 0b00000; // rx - currently unsupported.
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let Inst{5} = u;
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let Inst{4} = h;
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let Inst{3} = 0b0;
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let Inst{2-0} = sel;
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}
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class SPECIAL3_MT_FORK : MipsMTInst {
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bits<32> Inst;
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@ -6,13 +6,6 @@
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the MIPS MT ASE as defined by MD00378 1.12.
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//
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// TODO: Add support for the microMIPS encodings for the MT ASE and add the
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// instruction mappings.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MIPS MT Instruction Encodings
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@ -34,10 +27,6 @@ class FORK_ENC : SPECIAL3_MT_FORK;
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class YIELD_ENC : SPECIAL3_MT_YIELD;
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class MFTR_ENC : COP0_MFTTR_MT<FIELD5_MFTR>;
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class MTTR_ENC : COP0_MFTTR_MT<FIELD5_MTTR>;
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//===----------------------------------------------------------------------===//
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// MIPS MT Instruction Descriptions
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//===----------------------------------------------------------------------===//
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@ -50,22 +39,6 @@ class MT_1R_DESC_BASE<string instr_asm, InstrItinClass Itin = NoItinerary> {
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InstrItinClass Itinerary = Itin;
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}
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class MFTR_DESC {
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dag OutOperandList = (outs GPR32Opnd:$rd);
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dag InOperandList = (ins GPR32Opnd:$rt, uimm1:$u, uimm3:$sel, uimm1:$h);
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string AsmString = "mftr\t$rd, $rt, $u, $sel, $h";
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list<dag> Pattern = [];
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InstrItinClass Itinerary = II_MFTR;
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}
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class MTTR_DESC {
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dag OutOperandList = (outs GPR32Opnd:$rd);
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dag InOperandList = (ins GPR32Opnd:$rt, uimm1:$u, uimm3:$sel, uimm1:$h);
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string AsmString = "mttr\t$rt, $rd, $u, $sel, $h";
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list<dag> Pattern = [];
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InstrItinClass Itinerary = II_MTTR;
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}
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class FORK_DESC {
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dag OutOperandList = (outs GPR32Opnd:$rs, GPR32Opnd:$rd);
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dag InOperandList = (ins GPR32Opnd:$rt);
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@ -106,73 +79,8 @@ let hasSideEffects = 1, isNotDuplicable = 1,
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def FORK : FORK_ENC, FORK_DESC, ASE_MT;
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def YIELD : YIELD_ENC, YIELD_DESC, ASE_MT;
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def MFTR : MFTR_ENC, MFTR_DESC, ASE_MT;
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def MTTR : MTTR_ENC, MTTR_DESC, ASE_MT;
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}
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//===----------------------------------------------------------------------===//
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// MIPS MT Pseudo Instructions - used to support mtfr & mttr aliases.
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//===----------------------------------------------------------------------===//
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def MFTC0 : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins COP0Opnd:$rt,
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uimm3:$sel),
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"mftc0 $rd, $rt, $sel">, ASE_MT;
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def MFTGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rt,
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uimm3:$sel),
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"mftgpr $rd, $rt">, ASE_MT;
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def MFTLO : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins ACC64DSPOpnd:$ac),
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"mftlo $rt, $ac">, ASE_MT;
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def MFTHI : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins ACC64DSPOpnd:$ac),
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"mfthi $rt, $ac">, ASE_MT;
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def MFTACX : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins ACC64DSPOpnd:$ac),
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"mftacx $rt, $ac">, ASE_MT;
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def MFTDSP : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins),
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"mftdsp $rt">, ASE_MT;
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def MFTC1 : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins FGR32Opnd:$ft),
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"mftc1 $rt, $ft">, ASE_MT;
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def MFTHC1 : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins FGR32Opnd:$ft),
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"mfthc1 $rt, $ft">, ASE_MT;
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def CFTC1 : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins FGRCCOpnd:$ft),
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"cftc1 $rt, $ft">, ASE_MT;
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def MTTC0 : MipsAsmPseudoInst<(outs COP0Opnd:$rd), (ins GPR32Opnd:$rt,
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uimm3:$sel),
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"mttc0 $rt, $rd, $sel">, ASE_MT;
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def MTTGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins GPR32Opnd:$rd),
|
||||
"mttgpr $rd, $rt">, ASE_MT;
|
||||
|
||||
def MTTLO : MipsAsmPseudoInst<(outs ACC64DSPOpnd:$ac), (ins GPR32Opnd:$rt),
|
||||
"mttlo $rt, $ac">, ASE_MT;
|
||||
|
||||
def MTTHI : MipsAsmPseudoInst<(outs ACC64DSPOpnd:$ac), (ins GPR32Opnd:$rt),
|
||||
"mtthi $rt, $ac">, ASE_MT;
|
||||
|
||||
def MTTACX : MipsAsmPseudoInst<(outs ACC64DSPOpnd:$ac), (ins GPR32Opnd:$rt),
|
||||
"mttacx $rt, $ac">, ASE_MT;
|
||||
|
||||
def MTTDSP : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rt),
|
||||
"mttdsp $rt">, ASE_MT;
|
||||
|
||||
def MTTC1 : MipsAsmPseudoInst<(outs FGR32Opnd:$ft), (ins GPR32Opnd:$rt),
|
||||
"mttc1 $rt, $ft">, ASE_MT;
|
||||
|
||||
def MTTHC1 : MipsAsmPseudoInst<(outs FGR32Opnd:$ft), (ins GPR32Opnd:$rt),
|
||||
"mtthc1 $rt, $ft">, ASE_MT;
|
||||
|
||||
def CTTC1 : MipsAsmPseudoInst<(outs FGRCCOpnd:$ft), (ins GPR32Opnd:$rt),
|
||||
"cttc1 $rt, $ft">, ASE_MT;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// MIPS MT Instruction Definitions
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -187,22 +95,4 @@ let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def : MipsInstAlias<"evpe", (EVPE ZERO), 1>, ASE_MT;
|
||||
|
||||
def : MipsInstAlias<"yield $rs", (YIELD ZERO, GPR32Opnd:$rs), 1>, ASE_MT;
|
||||
|
||||
def : MipsInstAlias<"mftc0 $rd, $rt", (MFTC0 GPR32Opnd:$rd, COP0Opnd:$rt, 0),
|
||||
1>, ASE_MT;
|
||||
|
||||
def : MipsInstAlias<"mftlo $rt", (MFTLO GPR32Opnd:$rt, AC0), 1>, ASE_MT;
|
||||
|
||||
def : MipsInstAlias<"mfthi $rt", (MFTHI GPR32Opnd:$rt, AC0), 1>, ASE_MT;
|
||||
|
||||
def : MipsInstAlias<"mftacx $rt", (MFTACX GPR32Opnd:$rt, AC0), 1>, ASE_MT;
|
||||
|
||||
def : MipsInstAlias<"mttc0 $rd, $rt", (MTTC0 COP0Opnd:$rt, GPR32Opnd:$rd, 0),
|
||||
1>, ASE_MT;
|
||||
|
||||
def : MipsInstAlias<"mttlo $rt", (MTTLO AC0, GPR32Opnd:$rt), 1>, ASE_MT;
|
||||
|
||||
def : MipsInstAlias<"mtthi $rt", (MTTHI AC0, GPR32Opnd:$rt), 1>, ASE_MT;
|
||||
|
||||
def : MipsInstAlias<"mttacx $rt", (MTTACX AC0, GPR32Opnd:$rt), 1>, ASE_MT;
|
||||
}
|
||||
|
||||
@ -226,7 +226,6 @@ def II_MFC1 : InstrItinClass;
|
||||
def II_MFHC1 : InstrItinClass;
|
||||
def II_MFC2 : InstrItinClass;
|
||||
def II_MFHI_MFLO : InstrItinClass; // mfhi and mflo
|
||||
def II_MFTR : InstrItinClass;
|
||||
def II_MOD : InstrItinClass;
|
||||
def II_MODU : InstrItinClass;
|
||||
def II_MOVE : InstrItinClass;
|
||||
@ -256,7 +255,6 @@ def II_MTC1 : InstrItinClass;
|
||||
def II_MTHC1 : InstrItinClass;
|
||||
def II_MTC2 : InstrItinClass;
|
||||
def II_MTHI_MTLO : InstrItinClass; // mthi and mtlo
|
||||
def II_MTTR : InstrItinClass;
|
||||
def II_MUL : InstrItinClass;
|
||||
def II_MUH : InstrItinClass;
|
||||
def II_MUHU : InstrItinClass;
|
||||
@ -666,14 +664,12 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
|
||||
InstrItinData<II_MFHC0 , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_MFC1 , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_MFC2 , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_MFTR , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_MTC0 , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_MTHC0 , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_MTC1 , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_MTC2 , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_MFHC1 , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_MTHC1 , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_MTTR , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_CACHE , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_PREF , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_CACHEE , [InstrStage<1, [ALU]>]>,
|
||||
|
||||
@ -119,9 +119,6 @@ public:
|
||||
SMLoc IDLoc, const MCSubtargetInfo *STI);
|
||||
void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
|
||||
SMLoc IDLoc, const MCSubtargetInfo *STI);
|
||||
void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
|
||||
int16_t Imm1, int16_t Imm2, SMLoc IDLoc,
|
||||
const MCSubtargetInfo *STI);
|
||||
void emitAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg, bool Is64Bit,
|
||||
const MCSubtargetInfo *STI);
|
||||
void emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount,
|
||||
|
||||
@ -10,23 +10,4 @@
|
||||
0x08 0x10 0x65 0x7c # CHECK: fork $2, $3, $5
|
||||
0x09 0x00 0x80 0x7c # CHECK: yield $4
|
||||
0x09 0x20 0xa0 0x7c # CHECK: yield $4, $5
|
||||
0x02 0x20 0x05 0x41 # CHECK: mftr $4, $5, 0, 2, 0
|
||||
0x20 0x20 0x05 0x41 # CHECK: mftr $4, $5, 1, 0, 0
|
||||
0x21 0x20 0x00 0x41 # CHECK: mftr $4, $zero, 1, 1, 0
|
||||
0x21 0x20 0x0a 0x41 # CHECK: mftr $4, $10, 1, 1, 0
|
||||
0x22 0x20 0x0a 0x41 # CHECK: mftr $4, $10, 1, 2, 0
|
||||
0x32 0x20 0x0a 0x41 # CHECK: mftr $4, $10, 1, 2, 1
|
||||
0x23 0x20 0x1a 0x41 # CHECK: mftr $4, $26, 1, 3, 0
|
||||
0x23 0x20 0x1f 0x41 # CHECK: mftr $4, $ra, 1, 3, 0
|
||||
0x24 0x20 0x0e 0x41 # CHECK: mftr $4, $14, 1, 4, 0
|
||||
0x25 0x20 0x0f 0x41 # CHECK: mftr $4, $15, 1, 5, 0
|
||||
0x02 0x28 0x84 0x41 # CHECK: mttr $4, $5, 0, 2, 0
|
||||
0x20 0x28 0x84 0x41 # CHECK: mttr $4, $5, 1, 0, 0
|
||||
0x21 0x00 0x84 0x41 # CHECK: mttr $4, $zero, 1, 1, 0
|
||||
0x21 0x50 0x84 0x41 # CHECK: mttr $4, $10, 1, 1, 0
|
||||
0x22 0x50 0x84 0x41 # CHECK: mttr $4, $10, 1, 2, 0
|
||||
0x32 0x50 0x84 0x41 # CHECK: mttr $4, $10, 1, 2, 1
|
||||
0x23 0xd0 0x84 0x41 # CHECK: mttr $4, $26, 1, 3, 0
|
||||
0x23 0xf8 0x84 0x41 # CHECK: mttr $4, $ra, 1, 3, 0
|
||||
0x24 0x70 0x84 0x41 # CHECK: mttr $4, $14, 1, 4, 0
|
||||
0x25 0x78 0x84 0x41 # CHECK: mttr $4, $15, 1, 5, 0
|
||||
|
||||
|
||||
@ -10,23 +10,4 @@
|
||||
0x7c 0x65 0x10 0x08 # CHECK: fork $2, $3, $5
|
||||
0x7c 0x80 0x00 0x09 # CHECK: yield $4
|
||||
0x7c 0xa0 0x20 0x09 # CHECK: yield $4, $5
|
||||
0x41 0x05 0x20 0x02 # CHECK: mftr $4, $5, 0, 2, 0
|
||||
0x41 0x05 0x20 0x20 # CHECK: mftr $4, $5, 1, 0, 0
|
||||
0x41 0x00 0x20 0x21 # CHECK: mftr $4, $zero, 1, 1, 0
|
||||
0x41 0x0a 0x20 0x21 # CHECK: mftr $4, $10, 1, 1, 0
|
||||
0x41 0x0a 0x20 0x22 # CHECK: mftr $4, $10, 1, 2, 0
|
||||
0x41 0x0a 0x20 0x32 # CHECK: mftr $4, $10, 1, 2, 1
|
||||
0x41 0x1a 0x20 0x23 # CHECK: mftr $4, $26, 1, 3, 0
|
||||
0x41 0x1f 0x20 0x23 # CHECK: mftr $4, $ra, 1, 3, 0
|
||||
0x41 0x0e 0x20 0x24 # CHECK: mftr $4, $14, 1, 4, 0
|
||||
0x41 0x0f 0x20 0x25 # CHECK: mftr $4, $15, 1, 5, 0
|
||||
0x41 0x84 0x28 0x02 # CHECK: mttr $4, $5, 0, 2, 0
|
||||
0x41 0x84 0x28 0x20 # CHECK: mttr $4, $5, 1, 0, 0
|
||||
0x41 0x84 0x00 0x21 # CHECK: mttr $4, $zero, 1, 1, 0
|
||||
0x41 0x84 0x50 0x21 # CHECK: mttr $4, $10, 1, 1, 0
|
||||
0x41 0x84 0x50 0x22 # CHECK: mttr $4, $10, 1, 2, 0
|
||||
0x41 0x84 0x50 0x32 # CHECK: mttr $4, $10, 1, 2, 1
|
||||
0x41 0x84 0xd0 0x23 # CHECK: mttr $4, $26, 1, 3, 0
|
||||
0x41 0x84 0xf8 0x23 # CHECK: mttr $4, $ra, 1, 3, 0
|
||||
0x41 0x84 0x70 0x24 # CHECK: mttr $4, $14, 1, 4, 0
|
||||
0x41 0x84 0x78 0x25 # CHECK: mttr $4, $15, 1, 5, 0
|
||||
|
||||
|
||||
@ -1,3 +0,0 @@
|
||||
# RUN: not llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt < %s 2>&1 | FileCheck %s
|
||||
mftr 0($4), $5, 0, 0, 0 # CHECK: error: unexpected token in argument list
|
||||
mttr 0($4), $5, 0, 0, 0 # CHECK: error: unexpected token in argument list
|
||||
@ -1,27 +1,13 @@
|
||||
# RUN: not llvm-mc -arch=mips -mcpu=mips32 -mattr=+mt < %s 2>&1 | FileCheck %s
|
||||
dmt 4 # CHECK: error: invalid operand for instruction
|
||||
dmt $4, $5 # CHECK: error: invalid operand for instruction
|
||||
dmt $5, 0($4) # CHECK: error: invalid operand for instruction
|
||||
emt 4 # CHECK: error: invalid operand for instruction
|
||||
emt $4, $5 # CHECK: error: invalid operand for instruction
|
||||
emt $5, 0($5) # CHECK: error: invalid operand for instruction
|
||||
dvpe 4 # CHECK: error: invalid operand for instruction
|
||||
dvpe $4, $5 # CHECK: error: invalid operand for instruction
|
||||
dvpe $5, 0($4) # CHECK: error: invalid operand for instruction
|
||||
evpe 4 # CHECK: error: invalid operand for instruction
|
||||
evpe $4, $5 # CHECK: error: invalid operand for instruction
|
||||
evpe $5, 0($5) # CHECK: error: invalid operand for instruction
|
||||
mftr $4, 0($5), 0, 0, 0 # CHECK: error: invalid operand for instruction
|
||||
mftr $4, $5, 2, 0, 0 # CHECK: error: expected 1-bit unsigned immediate
|
||||
mftr $4, $5, -1, 0, 0 # CHECK: error: expected 1-bit unsigned immediate
|
||||
mftr $4, $5, 0, 8, 0 # CHECK: error: expected 3-bit unsigned immediate
|
||||
mftr $4, $5, 0, -1, 0 # CHECK: error: expected 3-bit unsigned immediate
|
||||
mftr $4, $4, 0, 0, 2 # CHECK: error: expected 1-bit unsigned immediate
|
||||
mftr $4, $5, 0, 0, -1 # CHECK: error: expected 1-bit unsigned immediate
|
||||
mttr $4, 0($5), 0, 0, 0 # CHECK: error: invalid operand for instruction
|
||||
mttr $4, $5, 2, 0, 0 # CHECK: error: expected 1-bit unsigned immediate
|
||||
mttr $4, $5, -1, 0, 0 # CHECK: error: expected 1-bit unsigned immediate
|
||||
mttr $4, $5, 0, 8, 0 # CHECK: error: expected 3-bit unsigned immediate
|
||||
mttr $4, $5, 0, -1, 0 # CHECK: error: expected 3-bit unsigned immediate
|
||||
mttr $4, $4, 0, 0, 2 # CHECK: error: expected 1-bit unsigned immediate
|
||||
mttr $4, $5, 0, 0, -1 # CHECK: error: expected 1-bit unsigned immediate
|
||||
dmt 4 # CHECK: error: invalid operand for instruction
|
||||
dmt $4, $5 # CHECK: error: invalid operand for instruction
|
||||
dmt $5, 0($4) # CHECK: error: invalid operand for instruction
|
||||
emt 4 # CHECK: error: invalid operand for instruction
|
||||
emt $4, $5 # CHECK: error: invalid operand for instruction
|
||||
emt $5, 0($5) # CHECK: error: invalid operand for instruction
|
||||
dvpe 4 # CHECK: error: invalid operand for instruction
|
||||
dvpe $4, $5 # CHECK: error: invalid operand for instruction
|
||||
dvpe $5, 0($4) # CHECK: error: invalid operand for instruction
|
||||
evpe 4 # CHECK: error: invalid operand for instruction
|
||||
evpe $4, $5 # CHECK: error: invalid operand for instruction
|
||||
evpe $5, 0($5) # CHECK: error: invalid operand for instruction
|
||||
|
||||
@ -1,18 +0,0 @@
|
||||
# RUN: not llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s \
|
||||
# RUN: 2>&1 | FileCheck %s
|
||||
|
||||
# The integrated assembler produces a wrong or misleading error message.
|
||||
|
||||
mftc0 0($4), $5 # CHECK: error: unexpected token in argument list
|
||||
mftc0 0($4), $5, 1 # CHECK: error: unexpected token in argument list
|
||||
mftgpr 0($4), $5 # CHECK: error: unexpected token in argument list
|
||||
mftlo 0($3) # CHECK: error: unexpected token in argument list
|
||||
mftlo 0($3), $ac1 # CHECK: error: unexpected token in argument list
|
||||
mfthi 0($3) # CHECK: error: unexpected token in argument list
|
||||
mfthi 0($3), $ac1 # CHECK: error: unexpected token in argument list
|
||||
mftacx 0($3) # CHECK: error: unexpected token in argument list
|
||||
mftacx 0($3), $ac1 # CHECK: error: unexpected token in argument list
|
||||
mftdsp 0($4) # CHECK: error: unexpected token in argument list
|
||||
mftc1 0($4), $f4 # CHECK: error: unexpected token in argument list
|
||||
mfthc1 0($4), $f4 # CHECK: error: unexpected token in argument list
|
||||
cftc1 0($4), $f8 # CHECK: error: unexpected token in argument list
|
||||
@ -1,23 +0,0 @@
|
||||
# RUN: not llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s \
|
||||
# RUN: 2>&1 | FileCheck %s
|
||||
|
||||
mftc0 $4, 0($5) # CHECK: error: invalid operand for instruction
|
||||
mftc0 $4, 0($5), 1 # CHECK: error: invalid operand for instruction
|
||||
mftc0 $4, $5, -1 # CHECK: error: expected 3-bit unsigned immediate
|
||||
mftc0 $4, $5, 9 # CHECK: error: expected 3-bit unsigned immediate
|
||||
mftc0 $4, $5, $6 # CHECK: error: expected 3-bit unsigned immediate
|
||||
mftgpr $4, 0($5) # CHECK: error: invalid operand for instruction
|
||||
mftgpr $4, $5, $6 # CHECK: error: invalid operand for instruction
|
||||
mftlo $3, 0($ac1) # CHECK: error: invalid operand for instruction
|
||||
mftlo $4, $ac1, $4 # CHECK: error: invalid operand for instruction
|
||||
mfthi $3, 0($ac1) # CHECK: error: invalid operand for instruction
|
||||
mfthi $4, $ac1, $4 # CHECK: error: invalid operand for instruction
|
||||
mftacx $3, 0($ac1) # CHECK: error: invalid operand for instruction
|
||||
mftacx $4, $ac1, $4 # CHECK: error: invalid operand for instruction
|
||||
mftdsp $4, $5 # CHECK: error: invalid operand for instruction
|
||||
mftdsp $4, $f5 # CHECK: error: invalid operand for instruction
|
||||
mftdsp $4, $ac0 # CHECK: error: invalid operand for instruction
|
||||
mftc1 $4, 0($f4) # CHECK: error: invalid operand for instruction
|
||||
mfthc1 $4, 0($f4) # CHECK: error: invalid operand for instruction
|
||||
cftc1 $4, 0($f4) # CHECK: error: invalid operand for instruction
|
||||
cftc1 $4, $f4, $5 # CHECK: error: invalid operand for instruction
|
||||
@ -1,47 +0,0 @@
|
||||
# RUN: llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s | FileCheck %s
|
||||
|
||||
# Check the various aliases of the m[ft]tr instruction.
|
||||
|
||||
mftc0 $4, $5 # CHECK: mftr $4, $5, 0, 0, 0 # encoding: [0x41,0x05,0x20,0x00]
|
||||
mftc0 $6, $7, 1 # CHECK: mftr $6, $7, 0, 1, 0 # encoding: [0x41,0x07,0x30,0x01]
|
||||
mftgpr $5, $9 # CHECK: mftr $5, $9, 1, 0, 0 # encoding: [0x41,0x09,0x28,0x20]
|
||||
mftlo $3 # CHECK: mftr $3, $zero, 1, 1, 0 # encoding: [0x41,0x00,0x18,0x21]
|
||||
mftlo $3, $ac0 # CHECK: mftr $3, $zero, 1, 1, 0 # encoding: [0x41,0x00,0x18,0x21]
|
||||
mftlo $3, $ac1 # CHECK: mftr $3, $4, 1, 1, 0 # encoding: [0x41,0x04,0x18,0x21]
|
||||
mftlo $3, $ac2 # CHECK: mftr $3, $8, 1, 1, 0 # encoding: [0x41,0x08,0x18,0x21]
|
||||
mftlo $3, $ac3 # CHECK: mftr $3, $12, 1, 1, 0 # encoding: [0x41,0x0c,0x18,0x21]
|
||||
mfthi $3, $ac0 # CHECK: mftr $3, $1, 1, 1, 0 # encoding: [0x41,0x01,0x18,0x21]
|
||||
mfthi $3, $ac1 # CHECK: mftr $3, $5, 1, 1, 0 # encoding: [0x41,0x05,0x18,0x21]
|
||||
mfthi $3, $ac2 # CHECK: mftr $3, $9, 1, 1, 0 # encoding: [0x41,0x09,0x18,0x21]
|
||||
mfthi $3, $ac3 # CHECK: mftr $3, $13, 1, 1, 0 # encoding: [0x41,0x0d,0x18,0x21]
|
||||
mftacx $3, $ac0 # CHECK: mftr $3, $2, 1, 1, 0 # encoding: [0x41,0x02,0x18,0x21]
|
||||
mftacx $3, $ac1 # CHECK: mftr $3, $6, 1, 1, 0 # encoding: [0x41,0x06,0x18,0x21]
|
||||
mftacx $3, $ac2 # CHECK: mftr $3, $10, 1, 1, 0 # encoding: [0x41,0x0a,0x18,0x21]
|
||||
mftacx $3, $ac3 # CHECK: mftr $3, $14, 1, 1, 0 # encoding: [0x41,0x0e,0x18,0x21]
|
||||
mftdsp $4 # CHECK: mftr $4, $16, 1, 1, 0 # encoding: [0x41,0x10,0x20,0x21]
|
||||
mftc1 $4, $f5 # CHECK: mftr $4, $5, 1, 2, 0 # encoding: [0x41,0x05,0x20,0x22]
|
||||
mfthc1 $4, $f5 # CHECK: mftr $4, $5, 1, 2, 1 # encoding: [0x41,0x05,0x20,0x32]
|
||||
cftc1 $4, $f9 # CHECK: mftr $4, $9, 1, 3, 0 # encoding: [0x41,0x09,0x20,0x23]
|
||||
|
||||
mttc0 $4, $5 # CHECK: mttr $4, $5, 0, 0, 0 # encoding: [0x41,0x84,0x28,0x00]
|
||||
mttc0 $6, $7, 1 # CHECK: mttr $6, $7, 0, 1, 0 # encoding: [0x41,0x86,0x38,0x01]
|
||||
mttgpr $5, $9 # CHECK: mttr $5, $9, 1, 0, 0 # encoding: [0x41,0x85,0x48,0x20]
|
||||
mttlo $3 # CHECK: mttr $3, $zero, 1, 1, 0 # encoding: [0x41,0x83,0x00,0x21]
|
||||
mttlo $3, $ac0 # CHECK: mttr $3, $zero, 1, 1, 0 # encoding: [0x41,0x83,0x00,0x21]
|
||||
mttlo $3, $ac1 # CHECK: mttr $3, $4, 1, 1, 0 # encoding: [0x41,0x83,0x20,0x21]
|
||||
mttlo $3, $ac2 # CHECK: mttr $3, $8, 1, 1, 0 # encoding: [0x41,0x83,0x40,0x21]
|
||||
mttlo $3, $ac3 # CHECK: mttr $3, $12, 1, 1, 0 # encoding: [0x41,0x83,0x60,0x21]
|
||||
mtthi $3 # CHECK: mttr $3, $1, 1, 1, 0 # encoding: [0x41,0x83,0x08,0x21]
|
||||
mtthi $3, $ac0 # CHECK: mttr $3, $1, 1, 1, 0 # encoding: [0x41,0x83,0x08,0x21]
|
||||
mtthi $3, $ac1 # CHECK: mttr $3, $5, 1, 1, 0 # encoding: [0x41,0x83,0x28,0x21]
|
||||
mtthi $3, $ac2 # CHECK: mttr $3, $9, 1, 1, 0 # encoding: [0x41,0x83,0x48,0x21]
|
||||
mtthi $3, $ac3 # CHECK: mttr $3, $13, 1, 1, 0 # encoding: [0x41,0x83,0x68,0x21]
|
||||
mttacx $3 # CHECK: mttr $3, $2, 1, 1, 0 # encoding: [0x41,0x83,0x10,0x21]
|
||||
mttacx $3, $ac0 # CHECK: mttr $3, $2, 1, 1, 0 # encoding: [0x41,0x83,0x10,0x21]
|
||||
mttacx $3, $ac1 # CHECK: mttr $3, $6, 1, 1, 0 # encoding: [0x41,0x83,0x30,0x21]
|
||||
mttacx $3, $ac2 # CHECK: mttr $3, $10, 1, 1, 0 # encoding: [0x41,0x83,0x50,0x21]
|
||||
mttacx $3, $ac3 # CHECK: mttr $3, $14, 1, 1, 0 # encoding: [0x41,0x83,0x70,0x21]
|
||||
mttdsp $4 # CHECK: mttr $4, $16, 1, 1, 0 # encoding: [0x41,0x84,0x80,0x21]
|
||||
mttc1 $4, $f5 # CHECK: mttr $4, $5, 1, 2, 0 # encoding: [0x41,0x84,0x28,0x22]
|
||||
mtthc1 $4, $f5 # CHECK: mttr $4, $5, 1, 2, 1 # encoding: [0x41,0x84,0x28,0x32]
|
||||
cttc1 $4, $f9 # CHECK: mttr $4, $9, 1, 3, 0 # encoding: [0x41,0x84,0x48,0x23]
|
||||
@ -1,8 +0,0 @@
|
||||
# RUN: llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s | FileCheck %s
|
||||
|
||||
# The selector value and register values here are marked as reserved in the
|
||||
# documentation, but GAS accepts them without warning.
|
||||
mftr $31, $31, 1, 1, 0 # CHECK: mftr $ra, $ra, 1, 1, 0 # encoding: [0x41,0x1f,0xf8,0x21]
|
||||
mttr $31, $31, 1, 1, 0 # CHECK: mttr $ra, $ra, 1, 1, 0 # encoding: [0x41,0x9f,0xf8,0x21]
|
||||
mftr $31, $13, 1, 6, 0 # CHECK: mftr $ra, $13, 1, 6, 0 # encoding: [0x41,0x0d,0xf8,0x26]
|
||||
mttr $31, $13, 1, 6, 0 # CHECK: mttr $ra, $13, 1, 6, 0 # encoding: [0x41,0x9f,0x68,0x26]
|
||||
@ -1,33 +1,13 @@
|
||||
# RUN: llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s \
|
||||
# RUN: | FileCheck %s
|
||||
dmt # CHECK: dmt # encoding: [0x41,0x60,0x0b,0xc1]
|
||||
dmt $5 # CHECK: dmt $5 # encoding: [0x41,0x65,0x0b,0xc1]
|
||||
emt # CHECK: emt # encoding: [0x41,0x60,0x0b,0xe1]
|
||||
emt $4 # CHECK: emt $4 # encoding: [0x41,0x64,0x0b,0xe1]
|
||||
dvpe # CHECK: dvpe # encoding: [0x41,0x60,0x00,0x01]
|
||||
dvpe $6 # CHECK: dvpe $6 # encoding: [0x41,0x66,0x00,0x01]
|
||||
evpe # CHECK: evpe # encoding: [0x41,0x60,0x00,0x21]
|
||||
evpe $4 # CHECK: evpe $4 # encoding: [0x41,0x64,0x00,0x21]
|
||||
fork $2, $3, $5 # CHECK: fork $2, $3, $5 # encoding: [0x7c,0x65,0x10,0x08]
|
||||
yield $4 # CHECK: yield $4 # encoding: [0x7c,0x80,0x00,0x09]
|
||||
yield $4, $5 # CHECK: yield $4, $5 # encoding: [0x7c,0xa0,0x20,0x09]
|
||||
mftr $4, $5, 0, 2, 0 # CHECK: mftr $4, $5, 0, 2, 0 # encoding: [0x41,0x05,0x20,0x02]
|
||||
mftr $4, $5, 1, 0, 0 # CHECK: mftr $4, $5, 1, 0, 0 # encoding: [0x41,0x05,0x20,0x20]
|
||||
mftr $4, $0, 1, 1, 0 # CHECK: mftr $4, $zero, 1, 1, 0 # encoding: [0x41,0x00,0x20,0x21]
|
||||
mftr $4, $10, 1, 1, 0 # CHECK: mftr $4, $10, 1, 1, 0 # encoding: [0x41,0x0a,0x20,0x21]
|
||||
mftr $4, $10, 1, 2, 0 # CHECK: mftr $4, $10, 1, 2, 0 # encoding: [0x41,0x0a,0x20,0x22]
|
||||
mftr $4, $10, 1, 2, 1 # CHECK: mftr $4, $10, 1, 2, 1 # encoding: [0x41,0x0a,0x20,0x32]
|
||||
mftr $4, $26, 1, 3, 0 # CHECK: mftr $4, $26, 1, 3, 0 # encoding: [0x41,0x1a,0x20,0x23]
|
||||
mftr $4, $31, 1, 3, 0 # CHECK: mftr $4, $ra, 1, 3, 0 # encoding: [0x41,0x1f,0x20,0x23]
|
||||
mftr $4, $14, 1, 4, 0 # CHECK: mftr $4, $14, 1, 4, 0 # encoding: [0x41,0x0e,0x20,0x24]
|
||||
mftr $4, $15, 1, 5, 0 # CHECK: mftr $4, $15, 1, 5, 0 # encoding: [0x41,0x0f,0x20,0x25]
|
||||
mttr $4, $5, 0, 2, 0 # CHECK: mttr $4, $5, 0, 2, 0 # encoding: [0x41,0x84,0x28,0x02]
|
||||
mttr $4, $5, 1, 0, 0 # CHECK: mttr $4, $5, 1, 0, 0 # encoding: [0x41,0x84,0x28,0x20]
|
||||
mttr $4, $0, 1, 1, 0 # CHECK: mttr $4, $zero, 1, 1, 0 # encoding: [0x41,0x84,0x00,0x21]
|
||||
mttr $4, $10, 1, 1, 0 # CHECK: mttr $4, $10, 1, 1, 0 # encoding: [0x41,0x84,0x50,0x21]
|
||||
mttr $4, $10, 1, 2, 0 # CHECK: mttr $4, $10, 1, 2, 0 # encoding: [0x41,0x84,0x50,0x22]
|
||||
mttr $4, $10, 1, 2, 1 # CHECK: mttr $4, $10, 1, 2, 1 # encoding: [0x41,0x84,0x50,0x32]
|
||||
mttr $4, $26, 1, 3, 0 # CHECK: mttr $4, $26, 1, 3, 0 # encoding: [0x41,0x84,0xd0,0x23]
|
||||
mttr $4, $31, 1, 3, 0 # CHECK: mttr $4, $ra, 1, 3, 0 # encoding: [0x41,0x84,0xf8,0x23]
|
||||
mttr $4, $14, 1, 4, 0 # CHECK: mttr $4, $14, 1, 4, 0 # encoding: [0x41,0x84,0x70,0x24]
|
||||
mttr $4, $15, 1, 5, 0 # CHECK: mttr $4, $15, 1, 5, 0 # encoding: [0x41,0x84,0x78,0x25]
|
||||
dmt # CHECK: dmt # encoding: [0x41,0x60,0x0b,0xc1]
|
||||
dmt $5 # CHECK: dmt $5 # encoding: [0x41,0x65,0x0b,0xc1]
|
||||
emt # CHECK: emt # encoding: [0x41,0x60,0x0b,0xe1]
|
||||
emt $4 # CHECK: emt $4 # encoding: [0x41,0x64,0x0b,0xe1]
|
||||
dvpe # CHECK: dvpe # encoding: [0x41,0x60,0x00,0x01]
|
||||
dvpe $6 # CHECK: dvpe $6 # encoding: [0x41,0x66,0x00,0x01]
|
||||
evpe # CHECK: evpe # encoding: [0x41,0x60,0x00,0x21]
|
||||
evpe $4 # CHECK: evpe $4 # encoding: [0x41,0x64,0x00,0x21]
|
||||
fork $2, $3, $5 # CHECK: fork $2, $3, $5 # encoding: [0x7c,0x65,0x10,0x08]
|
||||
yield $4 # CHECK: yield $4 # encoding: [0x7c,0x80,0x00,0x09]
|
||||
yield $4, $5 # CHECK: yield $4, $5 # encoding: [0x7c,0xa0,0x20,0x09]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user