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Remove indirection of vector<T*> in favor of deque<T>

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222958 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Blaikie 2014-11-29 18:13:39 +00:00
parent 710cdf729f
commit e722713c0a
5 changed files with 101 additions and 112 deletions
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23
utils/TableGen/AsmMatcherEmitter.cpp
View File

@ -1080,8 +1080,7 @@ struct LessRegisterSet {
void AsmMatcherInfo::
buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters) {
const std::vector<CodeGenRegister*> &Registers =
Target.getRegBank().getRegisters();
const auto &Registers = Target.getRegBank().getRegisters();
ArrayRef<CodeGenRegisterClass*> RegClassList =
Target.getRegBank().getRegClasses();
@ -1104,12 +1103,12 @@ buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters) {
// a unique register set class), and build the mapping of registers to the set
// they should classify to.
std::map<Record*, RegisterSet> RegisterMap;
for (const CodeGenRegister *CGR : Registers) {
for (const CodeGenRegister &CGR : Registers) {
// Compute the intersection of all sets containing this register.
RegisterSet ContainingSet;
for (const RegisterSet &RS : RegisterSets) {
if (!RS.count(CGR->TheDef))
if (!RS.count(CGR.TheDef))
continue;
if (ContainingSet.empty()) {
@ -1127,7 +1126,7 @@ buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters) {
if (!ContainingSet.empty()) {
RegisterSets.insert(ContainingSet);
RegisterMap.insert(std::make_pair(CGR->TheDef, ContainingSet));
RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
}
}
@ -2142,16 +2141,14 @@ static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
raw_ostream &OS) {
// Construct the match list.
std::vector<StringMatcher::StringPair> Matches;
const std::vector<CodeGenRegister*> &Regs =
Target.getRegBank().getRegisters();
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister *Reg = Regs[i];
if (Reg->TheDef->getValueAsString("AsmName").empty())
const auto &Regs = Target.getRegBank().getRegisters();
for (const CodeGenRegister &Reg : Regs) {
if (Reg.TheDef->getValueAsString("AsmName").empty())
continue;
Matches.push_back(StringMatcher::StringPair(
Reg->TheDef->getValueAsString("AsmName"),
"return " + utostr(Reg->EnumValue) + ";"));
Matches.push_back(
StringMatcher::StringPair(Reg.TheDef->getValueAsString("AsmName"),
"return " + utostr(Reg.EnumValue) + ";"));
}
OS << "static unsigned MatchRegisterName(StringRef Name) {\n";

11
utils/TableGen/AsmWriterEmitter.cpp
View File

@ -524,12 +524,12 @@ static const char *getMinimalTypeForRange(uint64_t Range) {
static void
emitRegisterNameString(raw_ostream &O, StringRef AltName,
const std::vector<CodeGenRegister*> &Registers) {
const std::deque<CodeGenRegister> &Registers) {
SequenceToOffsetTable<std::string> StringTable;
SmallVector<std::string, 4> AsmNames(Registers.size());
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
const CodeGenRegister &Reg = *Registers[i];
std::string &AsmName = AsmNames[i];
unsigned i = 0;
for (const auto &Reg : Registers) {
std::string &AsmName = AsmNames[i++];
// "NoRegAltName" is special. We don't need to do a lookup for that,
// as it's just a reference to the default register name.
@ -580,8 +580,7 @@ emitRegisterNameString(raw_ostream &O, StringRef AltName,
void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
Record *AsmWriter = Target.getAsmWriter();
std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
const std::vector<CodeGenRegister*> &Registers =
Target.getRegBank().getRegisters();
const auto &Registers = Target.getRegBank().getRegisters();
std::vector<Record*> AltNameIndices = Target.getRegAltNameIndices();
bool hasAltNames = AltNameIndices.size() > 1;

68
utils/TableGen/CodeGenRegisters.cpp
View File

@ -936,7 +936,6 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) {
// Read in the register definitions.
std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
std::sort(Regs.begin(), Regs.end(), LessRecordRegister());
Registers.reserve(Regs.size());
// Assign the enumeration values.
for (unsigned i = 0, e = Regs.size(); i != e; ++i)
getReg(Regs[i]);
@ -958,32 +957,32 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) {
// Now all the registers are known. Build the object graph of explicit
// register-register references.
for (unsigned i = 0, e = Registers.size(); i != e; ++i)
Registers[i]->buildObjectGraph(*this);
for (auto &Reg : Registers)
Reg.buildObjectGraph(*this);
// Compute register name map.
for (unsigned i = 0, e = Registers.size(); i != e; ++i)
for (auto &Reg : Registers)
// FIXME: This could just be RegistersByName[name] = register, except that
// causes some failures in MIPS - perhaps they have duplicate register name
// entries? (or maybe there's a reason for it - I don't know much about this
// code, just drive-by refactoring)
RegistersByName.insert(std::make_pair(
Registers[i]->TheDef->getValueAsString("AsmName"), Registers[i]));
RegistersByName.insert(
std::make_pair(Reg.TheDef->getValueAsString("AsmName"), &Reg));
// Precompute all sub-register maps.
// This will create Composite entries for all inferred sub-register indices.
for (unsigned i = 0, e = Registers.size(); i != e; ++i)
Registers[i]->computeSubRegs(*this);
for (auto &Reg : Registers)
Reg.computeSubRegs(*this);
// Infer even more sub-registers by combining leading super-registers.
for (unsigned i = 0, e = Registers.size(); i != e; ++i)
if (Registers[i]->CoveredBySubRegs)
Registers[i]->computeSecondarySubRegs(*this);
for (auto &Reg : Registers)
if (Reg.CoveredBySubRegs)
Reg.computeSecondarySubRegs(*this);
// After the sub-register graph is complete, compute the topologically
// ordered SuperRegs list.
for (unsigned i = 0, e = Registers.size(); i != e; ++i)
Registers[i]->computeSuperRegs(*this);
for (auto &Reg : Registers)
Reg.computeSuperRegs(*this);
// Native register units are associated with a leaf register. They've all been
// discovered now.
@ -1010,7 +1009,6 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) {
}
CodeGenRegBank::~CodeGenRegBank() {
DeleteContainerPointers(Registers);
DeleteContainerPointers(RegClasses);
}
@ -1034,8 +1032,8 @@ CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
CodeGenRegister *&Reg = Def2Reg[Def];
if (Reg)
return Reg;
Reg = new CodeGenRegister(Def, Registers.size() + 1);
Registers.push_back(Reg);
Registers.emplace_back(Def, Registers.size() + 1);
Reg = &Registers.back();
return Reg;
}
@ -1126,21 +1124,19 @@ void CodeGenRegBank::computeComposites() {
// and many registers will share TopoSigs on regular architectures.
BitVector TopoSigs(getNumTopoSigs());
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
CodeGenRegister *Reg1 = Registers[i];
for (const auto &Reg1 : Registers) {
// Skip identical subreg structures already processed.
if (TopoSigs.test(Reg1->getTopoSig()))
if (TopoSigs.test(Reg1.getTopoSig()))
continue;
TopoSigs.set(Reg1->getTopoSig());
TopoSigs.set(Reg1.getTopoSig());
const CodeGenRegister::SubRegMap &SRM1 = Reg1->getSubRegs();
const CodeGenRegister::SubRegMap &SRM1 = Reg1.getSubRegs();
for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(),
e1 = SRM1.end(); i1 != e1; ++i1) {
CodeGenSubRegIndex *Idx1 = i1->first;
CodeGenRegister *Reg2 = i1->second;
// Ignore identity compositions.
if (Reg1 == Reg2)
if (&Reg1 == Reg2)
continue;
const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
// Try composing Idx1 with another SubRegIndex.
@ -1152,7 +1148,7 @@ void CodeGenRegBank::computeComposites() {
if (Reg2 == Reg3)
continue;
// OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
CodeGenSubRegIndex *Idx3 = Reg1->getSubRegIndex(Reg3);
CodeGenSubRegIndex *Idx3 = Reg1.getSubRegIndex(Reg3);
assert(Idx3 && "Sub-register doesn't have an index");
// Conflicting composition? Emit a warning but allow it.
@ -1246,10 +1242,10 @@ static void computeUberSets(std::vector<UberRegSet> &UberSets,
std::vector<UberRegSet*> &RegSets,
CodeGenRegBank &RegBank) {
const std::vector<CodeGenRegister*> &Registers = RegBank.getRegisters();
const auto &Registers = RegBank.getRegisters();
// The Register EnumValue is one greater than its index into Registers.
assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
assert(Registers.size() == Registers.back().EnumValue &&
"register enum value mismatch");
// For simplicitly make the SetID the same as EnumValue.
@ -1276,8 +1272,8 @@ static void computeUberSets(std::vector<UberRegSet> &UberSets,
}
}
// Combine non-allocatable regs.
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
unsigned RegNum = Registers[i]->EnumValue;
for (const auto &Reg : Registers) {
unsigned RegNum = Reg.EnumValue;
if (AllocatableRegs.count(RegNum))
continue;
@ -1291,17 +1287,17 @@ static void computeUberSets(std::vector<UberRegSet> &UberSets,
// Insert Registers into the UberSets formed by union-find.
// Do not resize after this.
UberSets.resize(UberSetIDs.getNumClasses());
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
const CodeGenRegister *Reg = Registers[i];
unsigned USetID = UberSetIDs[Reg->EnumValue];
unsigned i = 0;
for (const CodeGenRegister &Reg : Registers) {
unsigned USetID = UberSetIDs[Reg.EnumValue];
if (!USetID)
USetID = ZeroID;
else if (USetID == ZeroID)
USetID = 0;
UberRegSet *USet = &UberSets[USetID];
USet->Regs.insert(Reg);
RegSets[i] = USet;
USet->Regs.insert(&Reg);
RegSets[i++] = USet;
}
}
@ -1439,11 +1435,11 @@ void CodeGenRegBank::computeRegUnitWeights() {
for (bool Changed = true; Changed; ++NumIters) {
assert(NumIters <= NumNativeRegUnits && "Runaway register unit weights");
Changed = false;
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
for (auto &Reg : Registers) {
CodeGenRegister::RegUnitList NormalUnits;
std::set<unsigned> NormalRegs;
Changed |= normalizeWeight(Registers[i], UberSets, RegSets,
NormalRegs, NormalUnits, *this);
Changed |= normalizeWeight(&Reg, UberSets, RegSets, NormalRegs,
NormalUnits, *this);
}
}
}

4
utils/TableGen/CodeGenRegisters.h
View File

@ -459,7 +459,7 @@ namespace llvm {
ConcatIdxMap ConcatIdx;
// Registers.
std::vector<CodeGenRegister*> Registers;
std::deque<CodeGenRegister> Registers;
StringMap<CodeGenRegister*> RegistersByName;
DenseMap<Record*, CodeGenRegister*> Def2Reg;
unsigned NumNativeRegUnits;
@ -552,7 +552,7 @@ namespace llvm {
ConcatIdx.insert(std::make_pair(Parts, Idx));
}
const std::vector<CodeGenRegister*> &getRegisters() { return Registers; }
const std::deque<CodeGenRegister> &getRegisters() { return Registers; }
const StringMap<CodeGenRegister*> &getRegistersByName() {
return RegistersByName;
}

107
utils/TableGen/RegisterInfoEmitter.cpp
View File

@ -53,10 +53,10 @@ public:
void run(raw_ostream &o);
private:
void EmitRegMapping(raw_ostream &o,
const std::vector<CodeGenRegister*> &Regs, bool isCtor);
void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
bool isCtor);
void EmitRegMappingTables(raw_ostream &o,
const std::vector<CodeGenRegister*> &Regs,
const std::deque<CodeGenRegister> &Regs,
bool isCtor);
void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
const std::string &ClassName);
@ -68,12 +68,13 @@ private:
// runEnums - Print out enum values for all of the registers.
void RegisterInfoEmitter::runEnums(raw_ostream &OS,
CodeGenTarget &Target, CodeGenRegBank &Bank) {
const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
const auto &Registers = Bank.getRegisters();
// Register enums are stored as uint16_t in the tables. Make sure we'll fit.
assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
std::string Namespace =
Registers.front().TheDef->getValueAsString("Namespace");
emitSourceFileHeader("Target Register Enum Values", OS);
@ -90,10 +91,9 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS,
OS << "namespace " << Namespace << " {\n";
OS << "enum {\n NoRegister,\n";
for (unsigned i = 0, e = Registers.size(); i != e; ++i)
OS << " " << Registers[i]->getName() << " = " <<
Registers[i]->EnumValue << ",\n";
assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
for (const auto &Reg : Registers)
OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n";
assert(Registers.size() == Registers.back().EnumValue &&
"Register enum value mismatch!");
OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
OS << "};\n";
@ -318,18 +318,16 @@ EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
<< "}\n\n";
}
void
RegisterInfoEmitter::EmitRegMappingTables(raw_ostream &OS,
const std::vector<CodeGenRegister*> &Regs,
bool isCtor) {
void RegisterInfoEmitter::EmitRegMappingTables(
raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
// Collect all information about dwarf register numbers
typedef std::map<Record*, std::vector<int64_t>, LessRecordRegister> DwarfRegNumsMapTy;
DwarfRegNumsMapTy DwarfRegNums;
// First, just pull all provided information to the map
unsigned maxLength = 0;
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
Record *Reg = Regs[i]->TheDef;
for (auto &RE : Regs) {
Record *Reg = RE.TheDef;
std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
maxLength = std::max((size_t)maxLength, RegNums.size());
if (DwarfRegNums.count(Reg))
@ -347,7 +345,7 @@ RegisterInfoEmitter::EmitRegMappingTables(raw_ostream &OS,
for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
I->second.push_back(-1);
std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace");
OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n";
@ -395,8 +393,8 @@ RegisterInfoEmitter::EmitRegMappingTables(raw_ostream &OS,
}
}
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
Record *Reg = Regs[i]->TheDef;
for (auto &RE : Regs) {
Record *Reg = RE.TheDef;
const RecordVal *V = Reg->getValue("DwarfAlias");
if (!V || !V->getValue())
continue;
@ -443,15 +441,13 @@ RegisterInfoEmitter::EmitRegMappingTables(raw_ostream &OS,
}
}
void
RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
const std::vector<CodeGenRegister*> &Regs,
bool isCtor) {
void RegisterInfoEmitter::EmitRegMapping(
raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
// Emit the initializer so the tables from EmitRegMappingTables get wired up
// to the MCRegisterInfo object.
unsigned maxLength = 0;
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
Record *Reg = Regs[i]->TheDef;
for (auto &RE : Regs) {
Record *Reg = RE.TheDef;
maxLength = std::max((size_t)maxLength,
Reg->getValueAsListOfInts("DwarfNumbers").size());
}
@ -459,7 +455,7 @@ RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
if (!maxLength)
return;
std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace");
// Emit reverse information about the dwarf register numbers.
for (unsigned j = 0; j < 2; ++j) {
@ -705,7 +701,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
OS << "#undef GET_REGINFO_MC_DESC\n";
const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
const auto &Regs = RegBank.getRegisters();
auto &SubRegIndices = RegBank.getSubRegIndices();
// The lists of sub-registers and super-registers go in the same array. That
@ -728,27 +724,27 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
SequenceToOffsetTable<std::string> RegStrings;
// Precompute register lists for the SequenceToOffsetTable.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister *Reg = Regs[i];
RegStrings.add(Reg->getName());
unsigned i = 0;
for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) {
const auto &Reg = *I;
RegStrings.add(Reg.getName());
// Compute the ordered sub-register list.
SetVector<const CodeGenRegister*> SR;
Reg->addSubRegsPreOrder(SR, RegBank);
diffEncode(SubRegLists[i], Reg->EnumValue, SR.begin(), SR.end());
Reg.addSubRegsPreOrder(SR, RegBank);
diffEncode(SubRegLists[i], Reg.EnumValue, SR.begin(), SR.end());
DiffSeqs.add(SubRegLists[i]);
// Compute the corresponding sub-register indexes.
SubRegIdxVec &SRIs = SubRegIdxLists[i];
for (unsigned j = 0, je = SR.size(); j != je; ++j)
SRIs.push_back(Reg->getSubRegIndex(SR[j]));
SRIs.push_back(Reg.getSubRegIndex(SR[j]));
SubRegIdxSeqs.add(SRIs);
// Super-registers are already computed.
const RegVec &SuperRegList = Reg->getSuperRegs();
diffEncode(SuperRegLists[i], Reg->EnumValue,
SuperRegList.begin(), SuperRegList.end());
const RegVec &SuperRegList = Reg.getSuperRegs();
diffEncode(SuperRegLists[i], Reg.EnumValue, SuperRegList.begin(),
SuperRegList.end());
DiffSeqs.add(SuperRegLists[i]);
// Differentially encode the register unit list, seeded by register number.
@ -763,18 +759,20 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
//
// Check the neighboring registers for arithmetic progressions.
unsigned ScaleA = ~0u, ScaleB = ~0u;
ArrayRef<unsigned> RUs = Reg->getNativeRegUnits();
if (i > 0 && Regs[i-1]->getNativeRegUnits().size() == RUs.size())
ScaleB = RUs.front() - Regs[i-1]->getNativeRegUnits().front();
if (i+1 != Regs.size() &&
Regs[i+1]->getNativeRegUnits().size() == RUs.size())
ScaleA = Regs[i+1]->getNativeRegUnits().front() - RUs.front();
ArrayRef<unsigned> RUs = Reg.getNativeRegUnits();
if (I != Regs.begin() &&
std::prev(I)->getNativeRegUnits().size() == RUs.size())
ScaleB = RUs.front() - std::prev(I)->getNativeRegUnits().front();
if (std::next(I) != Regs.end() &&
std::next(I)->getNativeRegUnits().size() == RUs.size())
ScaleA = std::next(I)->getNativeRegUnits().front() - RUs.front();
unsigned Scale = std::min(ScaleB, ScaleA);
// Default the scale to 0 if it can't be encoded in 4 bits.
if (Scale >= 16)
Scale = 0;
RegUnitInitScale[i] = Scale;
DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg->EnumValue, RUs));
DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs));
++i;
}
// Compute the final layout of the sequence table.
@ -816,13 +814,13 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0 },\n";
// Emit the register descriptors now.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister *Reg = Regs[i];
OS << " { " << RegStrings.get(Reg->getName()) << ", "
<< DiffSeqs.get(SubRegLists[i]) << ", "
<< DiffSeqs.get(SuperRegLists[i]) << ", "
<< SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", "
<< (DiffSeqs.get(RegUnitLists[i])*16 + RegUnitInitScale[i]) << " },\n";
i = 0;
for (const auto &Reg : Regs) {
OS << " { " << RegStrings.get(Reg.getName()) << ", "
<< DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i])
<< ", " << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", "
<< (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << " },\n";
++i;
}
OS << "};\n\n"; // End of register descriptors...
@ -917,8 +915,8 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
OS << "RegEncodingTable[] = {\n";
// Add entry for NoRegister
OS << " 0,\n";
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
Record *Reg = Regs[i]->TheDef;
for (const auto &RE : Regs) {
Record *Reg = RE.TheDef;
BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding");
uint64_t Value = 0;
for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) {
@ -1215,9 +1213,8 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
<< TargetName << "RegInfoDesc[] = { // Extra Descriptors\n";
OS << " { 0, 0 },\n";
const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister &Reg = *Regs[i];
const auto &Regs = RegBank.getRegisters();
for (const auto &Reg : Regs) {
OS << " { ";
OS << Reg.CostPerUse << ", "
<< int(AllocatableRegs.count(Reg.TheDef)) << " },\n";