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Add implicit def / use operands to MachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31632 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -60,6 +60,7 @@ private:
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MachineOperandType opType:8; // Discriminate the union.
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bool IsDef : 1; // True if this is a def, false if this is a use.
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bool IsImp : 1; // True if this is an implicit def or use.
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/// offset - Offset to address of global or external, only valid for
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/// MO_GlobalAddress, MO_ExternalSym and MO_ConstantPoolIndex
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@ -78,6 +79,7 @@ public:
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Op.opType = MachineOperand::MO_Immediate;
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Op.contents.immedVal = Val;
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Op.IsDef = false;
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Op.IsImp = false;
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Op.offset = 0;
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return Op;
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}
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@ -85,6 +87,7 @@ public:
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const MachineOperand &operator=(const MachineOperand &MO) {
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contents = MO.contents;
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IsDef = MO.IsDef;
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IsImp = MO.IsImp;
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opType = MO.opType;
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offset = MO.offset;
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return *this;
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@ -173,6 +176,15 @@ public:
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IsDef = true;
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}
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bool isImplicit() const {
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assert(isRegister() && "Wrong MachineOperand accessor");
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return IsImp;
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}
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bool setImplicit() {
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assert(isRegister() && "Wrong MachineOperand accessor");
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IsImp = true;
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}
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/// getReg - Returns the register number.
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///
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unsigned getReg() const {
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@ -330,10 +342,11 @@ public:
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/// addRegOperand - Add a register operand.
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///
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void addRegOperand(unsigned Reg, bool IsDef) {
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MachineOperand &Op = AddNewOperand();
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void addRegOperand(unsigned Reg, bool IsDef, bool IsImp = false) {
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MachineOperand &Op = AddNewOperand(IsImp);
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Op.opType = MachineOperand::MO_Register;
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Op.IsDef = IsDef;
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Op.IsImp = IsImp;
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Op.contents.RegNo = Reg;
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Op.offset = 0;
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}
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@ -415,8 +428,8 @@ public:
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Operands.erase(Operands.begin()+i);
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}
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private:
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MachineOperand &AddNewOperand() {
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assert(!OperandsComplete() &&
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MachineOperand &AddNewOperand(bool IsImp = false) {
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assert((IsImp || !OperandsComplete()) &&
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"Trying to add an operand to a machine instr that is already done!");
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Operands.push_back(MachineOperand());
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return Operands.back();
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@ -33,8 +33,9 @@ public:
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/// addReg - Add a new virtual register operand...
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///
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const MachineInstrBuilder &addReg(int RegNo, bool isDef = false) const {
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MI->addRegOperand(RegNo, isDef);
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const MachineInstrBuilder &addReg(int RegNo, bool isDef = false,
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bool isImp = false) const {
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MI->addRegOperand(RegNo, isDef, isImp);
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return *this;
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}
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