From e8068692f924a1577075bd2d7b72b44820e0ffb2 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Mon, 10 Dec 2012 20:04:40 +0000 Subject: [PATCH] [mips] Set HWEncoding field of registers. Use delete function getMipsRegisterNumbering and use MCRegisterInfo::getEncodingValue instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169760 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h | 93 ------------------- .../Mips/MCTargetDesc/MipsMCCodeEmitter.cpp | 12 ++- lib/Target/Mips/MipsAsmPrinter.cpp | 4 +- lib/Target/Mips/MipsCodeEmitter.cpp | 2 +- lib/Target/Mips/MipsRegisterInfo.td | 49 ++++------ 5 files changed, 30 insertions(+), 130 deletions(-) diff --git a/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h b/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h index 94e0d20d883..7a55efd5c33 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h +++ b/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h @@ -121,99 +121,6 @@ namespace MipsII { }; } - -/// getMipsRegisterNumbering - Given the enum value for some register, -/// return the number that it corresponds to. -inline static unsigned getMipsRegisterNumbering(unsigned RegEnum) -{ - switch (RegEnum) { - case Mips::ZERO: case Mips::ZERO_64: case Mips::F0: case Mips::D0_64: - case Mips::D0: case Mips::FCC0: case Mips::AC0: - return 0; - case Mips::AT: case Mips::AT_64: case Mips::F1: case Mips::D1_64: - case Mips::AC1: - return 1; - case Mips::V0: case Mips::V0_64: case Mips::F2: case Mips::D2_64: - case Mips::D1: case Mips::AC2: - return 2; - case Mips::V1: case Mips::V1_64: case Mips::F3: case Mips::D3_64: - case Mips::AC3: - return 3; - case Mips::A0: case Mips::A0_64: case Mips::F4: case Mips::D4_64: - case Mips::D2: - return 4; - case Mips::A1: case Mips::A1_64: case Mips::F5: case Mips::D5_64: - return 5; - case Mips::A2: case Mips::A2_64: case Mips::F6: case Mips::D6_64: - case Mips::D3: - return 6; - case Mips::A3: case Mips::A3_64: case Mips::F7: case Mips::D7_64: - return 7; - case Mips::T0: case Mips::T0_64: case Mips::F8: case Mips::D8_64: - case Mips::D4: - return 8; - case Mips::T1: case Mips::T1_64: case Mips::F9: case Mips::D9_64: - return 9; - case Mips::T2: case Mips::T2_64: case Mips::F10: case Mips::D10_64: - case Mips::D5: - return 10; - case Mips::T3: case Mips::T3_64: case Mips::F11: case Mips::D11_64: - return 11; - case Mips::T4: case Mips::T4_64: case Mips::F12: case Mips::D12_64: - case Mips::D6: - return 12; - case Mips::T5: case Mips::T5_64: case Mips::F13: case Mips::D13_64: - return 13; - case Mips::T6: case Mips::T6_64: case Mips::F14: case Mips::D14_64: - case Mips::D7: - return 14; - case Mips::T7: case Mips::T7_64: case Mips::F15: case Mips::D15_64: - return 15; - case Mips::S0: case Mips::S0_64: case Mips::F16: case Mips::D16_64: - case Mips::D8: - return 16; - case Mips::S1: case Mips::S1_64: case Mips::F17: case Mips::D17_64: - return 17; - case Mips::S2: case Mips::S2_64: case Mips::F18: case Mips::D18_64: - case Mips::D9: - return 18; - case Mips::S3: case Mips::S3_64: case Mips::F19: case Mips::D19_64: - return 19; - case Mips::S4: case Mips::S4_64: case Mips::F20: case Mips::D20_64: - case Mips::D10: - return 20; - case Mips::S5: case Mips::S5_64: case Mips::F21: case Mips::D21_64: - return 21; - case Mips::S6: case Mips::S6_64: case Mips::F22: case Mips::D22_64: - case Mips::D11: - return 22; - case Mips::S7: case Mips::S7_64: case Mips::F23: case Mips::D23_64: - return 23; - case Mips::T8: case Mips::T8_64: case Mips::F24: case Mips::D24_64: - case Mips::D12: - return 24; - case Mips::T9: case Mips::T9_64: case Mips::F25: case Mips::D25_64: - return 25; - case Mips::K0: case Mips::K0_64: case Mips::F26: case Mips::D26_64: - case Mips::D13: - return 26; - case Mips::K1: case Mips::K1_64: case Mips::F27: case Mips::D27_64: - return 27; - case Mips::GP: case Mips::GP_64: case Mips::F28: case Mips::D28_64: - case Mips::D14: - return 28; - case Mips::SP: case Mips::SP_64: case Mips::F29: case Mips::D29_64: - case Mips::HWR29: - return 29; - case Mips::FP: case Mips::FP_64: case Mips::F30: case Mips::D30_64: - case Mips::D15: - return 30; - case Mips::RA: case Mips::RA_64: case Mips::F31: case Mips::D31_64: - return 31; - default: llvm_unreachable("Unknown register number!"); - } -} - inline static std::pair MipsGetSymAndOffset(const MCFixup &Fixup) { MCFixupKind FixupKind = Fixup.getKind(); diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp index da1e4552c9d..4b68b7e6fec 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -19,6 +19,7 @@ #include "llvm/ADT/APFloat.h" #include "llvm/ADT/Statistic.h" #include "llvm/MC/MCCodeEmitter.h" +#include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrInfo.h" @@ -33,11 +34,12 @@ class MipsMCCodeEmitter : public MCCodeEmitter { MipsMCCodeEmitter(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION; void operator=(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION; const MCInstrInfo &MCII; + MCContext &Ctx; bool IsLittleEndian; public: - MipsMCCodeEmitter(const MCInstrInfo &mcii, bool IsLittle) : - MCII(mcii), IsLittleEndian(IsLittle) {} + MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_, bool IsLittle) : + MCII(mcii), Ctx(Ctx_), IsLittleEndian(IsLittle) {} ~MipsMCCodeEmitter() {} @@ -93,7 +95,7 @@ MCCodeEmitter *llvm::createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, const MCSubtargetInfo &STI, MCContext &Ctx) { - return new MipsMCCodeEmitter(MCII, false); + return new MipsMCCodeEmitter(MCII, Ctx, false); } MCCodeEmitter *llvm::createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, @@ -101,7 +103,7 @@ MCCodeEmitter *llvm::createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, const MCSubtargetInfo &STI, MCContext &Ctx) { - return new MipsMCCodeEmitter(MCII, true); + return new MipsMCCodeEmitter(MCII, Ctx, true); } /// EncodeInstruction - Emit the instruction. @@ -200,7 +202,7 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl &Fixups) const { if (MO.isReg()) { unsigned Reg = MO.getReg(); - unsigned RegNo = getMipsRegisterNumbering(Reg); + unsigned RegNo = Ctx.getRegisterInfo().getEncodingValue(Reg); return RegNo; } else if (MO.isImm()) { return static_cast(MO.getImm()); diff --git a/lib/Target/Mips/MipsAsmPrinter.cpp b/lib/Target/Mips/MipsAsmPrinter.cpp index 6bce5d2be0f..edbffad3fd7 100644 --- a/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/lib/Target/Mips/MipsAsmPrinter.cpp @@ -139,7 +139,7 @@ void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) { if (Mips::CPURegsRegClass.contains(Reg)) break; - unsigned RegNum = getMipsRegisterNumbering(Reg); + unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg); if (Mips::AFGR64RegClass.contains(Reg)) { FPUBitmask |= (3 << RegNum); CSFPRegsSize += AFGR64RegSize; @@ -154,7 +154,7 @@ void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) { // Set CPU Bitmask. for (; i != e; ++i) { unsigned Reg = CSI[i].getReg(); - unsigned RegNum = getMipsRegisterNumbering(Reg); + unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg); CPUBitmask |= (1 << RegNum); } diff --git a/lib/Target/Mips/MipsCodeEmitter.cpp b/lib/Target/Mips/MipsCodeEmitter.cpp index 2942716dc20..932e6b3d1ef 100644 --- a/lib/Target/Mips/MipsCodeEmitter.cpp +++ b/lib/Target/Mips/MipsCodeEmitter.cpp @@ -209,7 +209,7 @@ unsigned MipsCodeEmitter::getSizeInsEncoding(const MachineInstr &MI, unsigned MipsCodeEmitter::getMachineOpValue(const MachineInstr &MI, const MachineOperand &MO) const { if (MO.isReg()) - return getMipsRegisterNumbering(MO.getReg()); + return TM.getRegisterInfo()->getEncodingValue(MO.getReg()); else if (MO.isImm()) return static_cast(MO.getImm()); else if (MO.isGlobal()) diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index 391c19e07e3..f07a10c3dde 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -19,52 +19,43 @@ def sub_hi : SubRegIndex; } // We have banks of 32 registers each. -class MipsReg : Register { - field bits<5> Num; +class MipsReg Enc, string n> : Register { + let HWEncoding = Enc; let Namespace = "Mips"; } -class MipsRegWithSubRegs subregs> +class MipsRegWithSubRegs Enc, string n, list subregs> : RegisterWithSubRegs { - field bits<5> Num; + let HWEncoding = Enc; let Namespace = "Mips"; } // Mips CPU Registers -class MipsGPRReg num, string n> : MipsReg { - let Num = num; -} +class MipsGPRReg Enc, string n> : MipsReg; // Mips 64-bit CPU Registers -class Mips64GPRReg num, string n, list subregs> - : MipsRegWithSubRegs { - let Num = num; +class Mips64GPRReg Enc, string n, list subregs> + : MipsRegWithSubRegs { let SubRegIndices = [sub_32]; } // Mips 32-bit FPU Registers -class FPR num, string n> : MipsReg { - let Num = num; -} +class FPR Enc, string n> : MipsReg; // Mips 64-bit (aliased) FPU Registers -class AFPR num, string n, list subregs> - : MipsRegWithSubRegs { - let Num = num; +class AFPR Enc, string n, list subregs> + : MipsRegWithSubRegs { let SubRegIndices = [sub_fpeven, sub_fpodd]; let CoveredBySubRegs = 1; } -class AFPR64 num, string n, list subregs> - : MipsRegWithSubRegs { - let Num = num; +class AFPR64 Enc, string n, list subregs> + : MipsRegWithSubRegs { let SubRegIndices = [sub_32]; } // Mips Hardware Registers -class HWR num, string n> : MipsReg { - let Num = num; -} +class HWR Enc, string n> : MipsReg; //===----------------------------------------------------------------------===// // Registers @@ -239,21 +230,21 @@ let Namespace = "Mips" in { def FCR31 : Register<"31">; // fcc0 register - def FCC0 : Register<"fcc0">; + def FCC0 : MipsReg<0, "fcc0">; // PC register def PC : Register<"pc">; // Hardware register $29 - def HWR29 : Register<"29">; - def HWR29_64 : Register<"29">; + def HWR29 : MipsReg<29, "29">; + def HWR29_64 : MipsReg<29, "29">; // Accum registers let SubRegIndices = [sub_lo, sub_hi] in - def AC0 : RegisterWithSubRegs<"ac0", [LO, HI]>; - def AC1 : Register<"ac1">; - def AC2 : Register<"ac2">; - def AC3 : Register<"ac3">; + def AC0 : MipsRegWithSubRegs<0, "ac0", [LO, HI]>; + def AC1 : MipsReg<1, "ac1">; + def AC2 : MipsReg<2, "ac2">; + def AC3 : MipsReg<3, "ac3">; def DSPCtrl : Register<"dspctrl">; }