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Supported lowerInterleavedStore() in X86InterleavedAccess.
Reviewers: RKSimon, DavidKreitzer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32658 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306068 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Farhana Aleen
parent
e1ae008085
commit
e83d2eccef
@ -1070,6 +1070,12 @@ namespace llvm {
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ArrayRef<unsigned> Indices,
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unsigned Factor) const override;
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/// \brief Lower interleaved store(s) into target specific
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/// instructions/intrinsics.
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bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
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unsigned Factor) const override;
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void finalizeLowering(MachineFunction &MF) const override;
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protected:
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@ -16,6 +16,7 @@
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#include "X86ISelLowering.h"
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#include "X86TargetMachine.h"
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#include "llvm/Analysis/VectorUtils.h"
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using namespace llvm;
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@ -50,9 +51,8 @@ class X86InterleavedAccessGroup {
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IRBuilder<> &Builder;
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/// \brief Breaks down a vector \p 'Inst' of N elements into \p NumSubVectors
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/// sub vectors of type \p T. Returns true and the sub-vectors in
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/// \p DecomposedVectors if it decomposes the Inst, returns false otherwise.
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bool decompose(Instruction *Inst, unsigned NumSubVectors, VectorType *T,
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/// sub vectors of type \p T. Returns the sub-vectors in \p DecomposedVectors.
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void decompose(Instruction *Inst, unsigned NumSubVectors, VectorType *T,
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SmallVectorImpl<Instruction *> &DecomposedVectors);
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/// \brief Performs matrix transposition on a 4x4 matrix \p InputVectors and
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@ -80,8 +80,7 @@ public:
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/// target information \p STarget.
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explicit X86InterleavedAccessGroup(Instruction *I,
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ArrayRef<ShuffleVectorInst *> Shuffs,
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ArrayRef<unsigned> Ind,
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const unsigned F,
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ArrayRef<unsigned> Ind, const unsigned F,
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const X86Subtarget &STarget,
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IRBuilder<> &B)
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: Inst(I), Shuffles(Shuffs), Indices(Ind), Factor(F), Subtarget(STarget),
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@ -102,48 +101,61 @@ bool X86InterleavedAccessGroup::isSupported() const {
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uint64_t ShuffleVecSize = DL.getTypeSizeInBits(ShuffleVecTy);
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Type *ShuffleEltTy = ShuffleVecTy->getVectorElementType();
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if (DL.getTypeSizeInBits(Inst->getType()) < Factor * ShuffleVecSize)
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return false;
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// Currently, lowering is supported for 4-element vectors of 64 bits on AVX.
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uint64_t ExpectedShuffleVecSize;
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if (isa<LoadInst>(Inst))
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ExpectedShuffleVecSize = 256;
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else
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ExpectedShuffleVecSize = 1024;
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// Currently, lowering is supported for 64 bits on AVX.
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if (!Subtarget.hasAVX() || ShuffleVecSize != 256 ||
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if (!Subtarget.hasAVX() || ShuffleVecSize != ExpectedShuffleVecSize ||
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DL.getTypeSizeInBits(ShuffleEltTy) != 64 || Factor != 4)
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return false;
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return true;
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}
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bool X86InterleavedAccessGroup::decompose(
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void X86InterleavedAccessGroup::decompose(
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Instruction *VecInst, unsigned NumSubVectors, VectorType *SubVecTy,
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SmallVectorImpl<Instruction *> &DecomposedVectors) {
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assert((isa<LoadInst>(VecInst) || isa<ShuffleVectorInst>(VecInst)) &&
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"Expected Load or Shuffle");
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Type *VecTy = VecInst->getType();
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(void)VecTy;
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assert(VecTy->isVectorTy() &&
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DL.getTypeSizeInBits(VecTy) >=
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DL.getTypeSizeInBits(SubVecTy) * NumSubVectors &&
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"Invalid Inst-size!!!");
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assert(VecTy->getVectorElementType() == SubVecTy->getVectorElementType() &&
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"Element type mismatched!!!");
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if (!isa<LoadInst>(VecInst))
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return false;
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if (auto *SVI = dyn_cast<ShuffleVectorInst>(VecInst)) {
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Value *Op0 = SVI->getOperand(0);
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Value *Op1 = SVI->getOperand(1);
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// Generate N(= NumSubVectors) shuffles of T(= SubVecTy) type.
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for (unsigned i = 0; i < NumSubVectors; ++i)
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DecomposedVectors.push_back(
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cast<ShuffleVectorInst>(Builder.CreateShuffleVector(
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Op0, Op1, createSequentialMask(Builder, Indices[i],
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SubVecTy->getVectorNumElements(), 0))));
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return;
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}
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// Decompose the load instruction.
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LoadInst *LI = cast<LoadInst>(VecInst);
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Type *VecBasePtrTy = SubVecTy->getPointerTo(LI->getPointerAddressSpace());
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Value *VecBasePtr =
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Builder.CreateBitCast(LI->getPointerOperand(), VecBasePtrTy);
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// Generate N loads of T type
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// Generate N loads of T type.
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for (unsigned i = 0; i < NumSubVectors; i++) {
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// TODO: Support inbounds GEP
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// TODO: Support inbounds GEP.
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Value *NewBasePtr = Builder.CreateGEP(VecBasePtr, Builder.getInt32(i));
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Instruction *NewLoad =
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Builder.CreateAlignedLoad(NewBasePtr, LI->getAlignment());
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DecomposedVectors.push_back(NewLoad);
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}
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return true;
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}
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void X86InterleavedAccessGroup::transpose_4x4(
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@ -181,21 +193,46 @@ void X86InterleavedAccessGroup::transpose_4x4(
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// instructions/intrinsics.
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bool X86InterleavedAccessGroup::lowerIntoOptimizedSequence() {
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SmallVector<Instruction *, 4> DecomposedVectors;
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VectorType *VecTy = Shuffles[0]->getType();
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// Try to generate target-sized register(/instruction).
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if (!decompose(Inst, Factor, VecTy, DecomposedVectors))
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return false;
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SmallVector<Value *, 4> TransposedVectors;
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// Perform matrix-transposition in order to compute interleaved
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// results by generating some sort of (optimized) target-specific
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// instructions.
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VectorType *ShuffleTy = Shuffles[0]->getType();
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if (isa<LoadInst>(Inst)) {
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// Try to generate target-sized register(/instruction).
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decompose(Inst, Factor, ShuffleTy, DecomposedVectors);
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// Perform matrix-transposition in order to compute interleaved
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// results by generating some sort of (optimized) target-specific
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// instructions.
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transpose_4x4(DecomposedVectors, TransposedVectors);
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// Now replace the unoptimized-interleaved-vectors with the
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// transposed-interleaved vectors.
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for (unsigned i = 0, e = Shuffles.size(); i < e; ++i)
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Shuffles[i]->replaceAllUsesWith(TransposedVectors[Indices[i]]);
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return true;
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}
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Type *ShuffleEltTy = ShuffleTy->getVectorElementType();
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unsigned NumSubVecElems = ShuffleTy->getVectorNumElements() / Factor;
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// Lower the interleaved stores:
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// 1. Decompose the interleaved wide shuffle into individual shuffle
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// vectors.
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decompose(Shuffles[0], Factor,
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VectorType::get(ShuffleEltTy, NumSubVecElems), DecomposedVectors);
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// 2. Transpose the interleaved-vectors into vectors of contiguous
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// elements.
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transpose_4x4(DecomposedVectors, TransposedVectors);
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// Now replace the unoptimized-interleaved-vectors with the
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// transposed-interleaved vectors.
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for (unsigned i = 0; i < Shuffles.size(); i++)
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Shuffles[i]->replaceAllUsesWith(TransposedVectors[Indices[i]]);
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// 3. Concatenate the contiguous-vectors back into a wide vector.
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Value *WideVec = concatenateVectors(Builder, TransposedVectors);
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// 4. Generate a store instruction for wide-vec.
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StoreInst *SI = cast<StoreInst>(Inst);
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Builder.CreateAlignedStore(WideVec, SI->getPointerOperand(),
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SI->getAlignment());
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return true;
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}
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@ -220,3 +257,30 @@ bool X86TargetLowering::lowerInterleavedLoad(
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return Grp.isSupported() && Grp.lowerIntoOptimizedSequence();
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}
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bool X86TargetLowering::lowerInterleavedStore(StoreInst *SI,
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ShuffleVectorInst *SVI,
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unsigned Factor) const {
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assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
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"Invalid interleave factor");
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VectorType *VecTy = SVI->getType();
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assert(VecTy->getVectorNumElements() % Factor == 0 &&
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"Invalid interleaved store");
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// Holds the indices of SVI that correspond to the starting index of each
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// interleaved shuffle.
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SmallVector<unsigned, 4> Indices;
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auto Mask = SVI->getShuffleMask();
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for (unsigned i = 0; i < Factor; i++)
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Indices.push_back(Mask[i]);
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ArrayRef<ShuffleVectorInst *> Shuffles = makeArrayRef(SVI);
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// Create an interleaved access group.
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IRBuilder<> Builder(SI);
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X86InterleavedAccessGroup Grp(SI, Shuffles, Indices, Factor, Subtarget,
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Builder);
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return Grp.isSupported() && Grp.lowerIntoOptimizedSequence();
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}
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@ -129,26 +129,18 @@ define <4 x i64> @load_factori64_4(<16 x i64>* %ptr) {
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define void @store_factorf64_4(<16 x double>* %ptr, <4 x double> %v0, <4 x double> %v1, <4 x double> %v2, <4 x double> %v3) {
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; AVX-LABEL: store_factorf64_4:
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; AVX: # BB#0:
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; AVX-NEXT: vunpcklpd {{.*#+}} xmm4 = xmm2[0],xmm3[0]
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; AVX-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm4
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; AVX-NEXT: vunpcklpd {{.*#+}} xmm5 = xmm0[0],xmm1[0]
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; AVX-NEXT: vblendpd {{.*#+}} ymm4 = ymm5[0,1],ymm4[2,3]
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; AVX-NEXT: vunpckhpd {{.*#+}} xmm5 = xmm2[1],xmm3[1]
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; AVX-NEXT: vinsertf128 $1, %xmm5, %ymm0, %ymm5
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; AVX-NEXT: vunpckhpd {{.*#+}} xmm6 = xmm0[1],xmm1[1]
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; AVX-NEXT: vblendpd {{.*#+}} ymm5 = ymm6[0,1],ymm5[2,3]
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; AVX-NEXT: vunpcklpd {{.*#+}} ymm6 = ymm2[0],ymm3[0],ymm2[2],ymm3[2]
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; AVX-NEXT: vunpcklpd {{.*#+}} ymm7 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
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; AVX-NEXT: vextractf128 $1, %ymm7, %xmm7
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; AVX-NEXT: vblendpd {{.*#+}} ymm6 = ymm7[0,1],ymm6[2,3]
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; AVX-NEXT: vunpckhpd {{.*#+}} ymm2 = ymm2[1],ymm3[1],ymm2[3],ymm3[3]
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; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm4
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; AVX-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm5
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; AVX-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm2[2,3]
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; AVX-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm1[2,3],ymm3[2,3]
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; AVX-NEXT: vunpcklpd {{.*#+}} ymm2 = ymm4[0],ymm5[0],ymm4[2],ymm5[2]
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; AVX-NEXT: vunpcklpd {{.*#+}} ymm3 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
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; AVX-NEXT: vunpckhpd {{.*#+}} ymm4 = ymm4[1],ymm5[1],ymm4[3],ymm5[3]
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; AVX-NEXT: vunpckhpd {{.*#+}} ymm0 = ymm0[1],ymm1[1],ymm0[3],ymm1[3]
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; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0
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; AVX-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm2[2,3]
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; AVX-NEXT: vmovupd %ymm0, 96(%rdi)
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; AVX-NEXT: vmovupd %ymm6, 64(%rdi)
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; AVX-NEXT: vmovupd %ymm5, 32(%rdi)
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; AVX-NEXT: vmovupd %ymm4, (%rdi)
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; AVX-NEXT: vmovupd %ymm3, 64(%rdi)
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; AVX-NEXT: vmovupd %ymm4, 32(%rdi)
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; AVX-NEXT: vmovupd %ymm2, (%rdi)
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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%s0 = shufflevector <4 x double> %v0, <4 x double> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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@ -161,55 +153,35 @@ define void @store_factorf64_4(<16 x double>* %ptr, <4 x double> %v0, <4 x doubl
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define void @store_factori64_4(<16 x i64>* %ptr, <4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, <4 x i64> %v3) {
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; AVX1-LABEL: store_factori64_4:
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; AVX1: # BB#0:
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; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm4 = xmm2[0],xmm3[0]
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; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm4
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; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm5 = xmm0[0],xmm1[0]
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; AVX1-NEXT: vblendpd {{.*#+}} ymm4 = ymm5[0,1],ymm4[2,3]
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; AVX1-NEXT: vpunpckhqdq {{.*#+}} xmm5 = xmm2[1],xmm3[1]
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; AVX1-NEXT: vinsertf128 $1, %xmm5, %ymm0, %ymm5
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; AVX1-NEXT: vpunpckhqdq {{.*#+}} xmm6 = xmm0[1],xmm1[1]
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; AVX1-NEXT: vblendpd {{.*#+}} ymm5 = ymm6[0,1],ymm5[2,3]
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; AVX1-NEXT: vunpcklpd {{.*#+}} ymm6 = ymm2[0],ymm3[0],ymm2[2],ymm3[2]
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; AVX1-NEXT: vunpcklpd {{.*#+}} ymm7 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
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; AVX1-NEXT: vextractf128 $1, %ymm7, %xmm7
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; AVX1-NEXT: vblendpd {{.*#+}} ymm6 = ymm7[0,1],ymm6[2,3]
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; AVX1-NEXT: vunpckhpd {{.*#+}} ymm2 = ymm2[1],ymm3[1],ymm2[3],ymm3[3]
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm4
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; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm5
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; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm2[2,3]
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; AVX1-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm1[2,3],ymm3[2,3]
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; AVX1-NEXT: vunpcklpd {{.*#+}} ymm2 = ymm4[0],ymm5[0],ymm4[2],ymm5[2]
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; AVX1-NEXT: vunpcklpd {{.*#+}} ymm3 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
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; AVX1-NEXT: vunpckhpd {{.*#+}} ymm4 = ymm4[1],ymm5[1],ymm4[3],ymm5[3]
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; AVX1-NEXT: vunpckhpd {{.*#+}} ymm0 = ymm0[1],ymm1[1],ymm0[3],ymm1[3]
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
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; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm2[2,3]
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; AVX1-NEXT: vmovupd %ymm0, 96(%rdi)
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; AVX1-NEXT: vmovupd %ymm6, 64(%rdi)
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; AVX1-NEXT: vmovupd %ymm5, 32(%rdi)
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; AVX1-NEXT: vmovupd %ymm4, (%rdi)
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; AVX1-NEXT: vmovupd %ymm3, 64(%rdi)
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; AVX1-NEXT: vmovupd %ymm4, 32(%rdi)
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; AVX1-NEXT: vmovupd %ymm2, (%rdi)
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; AVX1-NEXT: vzeroupper
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: store_factori64_4:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpunpcklqdq {{.*#+}} ymm4 = ymm2[0],ymm3[0],ymm2[2],ymm3[2]
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; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm5
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; AVX2-NEXT: vpermq {{.*#+}} ymm6 = ymm1[0,2,2,3]
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; AVX2-NEXT: vpblendd {{.*#+}} xmm5 = xmm5[0,1],xmm6[2,3]
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; AVX2-NEXT: vpblendd {{.*#+}} ymm4 = ymm5[0,1,2,3],ymm4[4,5,6,7]
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; AVX2-NEXT: vpunpckhqdq {{.*#+}} ymm5 = ymm2[1],ymm3[1],ymm2[3],ymm3[3]
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; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm6
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; AVX2-NEXT: vpermq {{.*#+}} ymm7 = ymm0[3,1,2,3]
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; AVX2-NEXT: vpblendd {{.*#+}} xmm6 = xmm7[0,1],xmm6[2,3]
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; AVX2-NEXT: vpblendd {{.*#+}} ymm5 = ymm6[0,1,2,3],ymm5[4,5,6,7]
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; AVX2-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm6
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; AVX2-NEXT: vpbroadcastq %xmm3, %ymm7
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; AVX2-NEXT: vpblendd {{.*#+}} ymm6 = ymm6[0,1,2,3,4,5],ymm7[6,7]
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; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm7 = xmm0[0],xmm1[0]
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; AVX2-NEXT: vpblendd {{.*#+}} ymm6 = ymm7[0,1,2,3],ymm6[4,5,6,7]
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; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm3
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; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,1,1,3]
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; AVX2-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3,4,5],ymm3[6,7]
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; AVX2-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
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; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm2[4,5,6,7]
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; AVX2-NEXT: vmovdqu %ymm0, 32(%rdi)
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; AVX2-NEXT: vmovdqu %ymm6, (%rdi)
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; AVX2-NEXT: vmovdqu %ymm5, 96(%rdi)
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; AVX2-NEXT: vmovdqu %ymm4, 64(%rdi)
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; AVX2-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm4
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; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm1, %ymm5
|
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; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],ymm2[2,3]
|
||||
; AVX2-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm1[2,3],ymm3[2,3]
|
||||
; AVX2-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm4[0],ymm5[0],ymm4[2],ymm5[2]
|
||||
; AVX2-NEXT: vpunpcklqdq {{.*#+}} ymm3 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
|
||||
; AVX2-NEXT: vpunpckhqdq {{.*#+}} ymm4 = ymm4[1],ymm5[1],ymm4[3],ymm5[3]
|
||||
; AVX2-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm0[1],ymm1[1],ymm0[3],ymm1[3]
|
||||
; AVX2-NEXT: vmovdqu %ymm0, 96(%rdi)
|
||||
; AVX2-NEXT: vmovdqu %ymm3, 64(%rdi)
|
||||
; AVX2-NEXT: vmovdqu %ymm4, 32(%rdi)
|
||||
; AVX2-NEXT: vmovdqu %ymm2, (%rdi)
|
||||
; AVX2-NEXT: vzeroupper
|
||||
; AVX2-NEXT: retq
|
||||
%s0 = shufflevector <4 x i64> %v0, <4 x i64> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
|
||||
@ -106,8 +106,22 @@ define void @store_factorf64_4(<16 x double>* %ptr, <4 x double> %v0, <4 x doubl
|
||||
; CHECK-LABEL: @store_factorf64_4(
|
||||
; CHECK-NEXT: [[S0:%.*]] = shufflevector <4 x double> [[V0:%.*]], <4 x double> [[V1:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
; CHECK-NEXT: [[S1:%.*]] = shufflevector <4 x double> [[V2:%.*]], <4 x double> [[V3:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <8 x double> [[S0]], <8 x double> [[S1]], <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>
|
||||
; CHECK-NEXT: store <16 x double> [[INTERLEAVED_VEC]], <16 x double>* [[PTR:%.*]], align 16
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x double> [[S0]], <8 x double> [[S1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x double> [[S0]], <8 x double> [[S1]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x double> [[S0]], <8 x double> [[S1]], <4 x i32> <i32 8, i32 9, i32 10, i32 11>
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x double> [[S0]], <8 x double> [[S1]], <4 x i32> <i32 12, i32 13, i32 14, i32 15>
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x double> [[TMP1]], <4 x double> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x double> [[TMP1]], <4 x double> [[TMP3]], <4 x i32> <i32 2, i32 3, i32 6, i32 7>
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> [[TMP4]], <4 x i32> <i32 2, i32 3, i32 6, i32 7>
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x double> [[TMP5]], <4 x double> [[TMP6]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <4 x double> [[TMP7]], <4 x double> [[TMP8]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x double> [[TMP5]], <4 x double> [[TMP6]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
||||
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <4 x double> [[TMP7]], <4 x double> [[TMP8]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
||||
; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x double> [[TMP9]], <4 x double> [[TMP11]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x double> [[TMP10]], <4 x double> [[TMP12]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
; CHECK-NEXT: [[TMP15:%.*]] = shufflevector <8 x double> [[TMP13]], <8 x double> [[TMP14]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
||||
; CHECK-NEXT: store <16 x double> [[TMP15]], <16 x double>* [[PTR:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
%s0 = shufflevector <4 x double> %v0, <4 x double> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
@ -121,8 +135,22 @@ define void @store_factori64_4(<16 x i64>* %ptr, <4 x i64> %v0, <4 x i64> %v1, <
|
||||
; CHECK-LABEL: @store_factori64_4(
|
||||
; CHECK-NEXT: [[S0:%.*]] = shufflevector <4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
; CHECK-NEXT: [[S1:%.*]] = shufflevector <4 x i64> [[V2:%.*]], <4 x i64> [[V3:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <8 x i64> [[S0]], <8 x i64> [[S1]], <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>
|
||||
; CHECK-NEXT: store <16 x i64> [[INTERLEAVED_VEC]], <16 x i64>* [[PTR:%.*]], align 16
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i64> [[S0]], <8 x i64> [[S1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i64> [[S0]], <8 x i64> [[S1]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i64> [[S0]], <8 x i64> [[S1]], <4 x i32> <i32 8, i32 9, i32 10, i32 11>
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i64> [[S0]], <8 x i64> [[S1]], <4 x i32> <i32 12, i32 13, i32 14, i32 15>
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i64> [[TMP1]], <4 x i64> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i64> [[TMP2]], <4 x i64> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i64> [[TMP1]], <4 x i64> [[TMP3]], <4 x i32> <i32 2, i32 3, i32 6, i32 7>
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i64> [[TMP2]], <4 x i64> [[TMP4]], <4 x i32> <i32 2, i32 3, i32 6, i32 7>
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x i64> [[TMP5]], <4 x i64> [[TMP6]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <4 x i64> [[TMP7]], <4 x i64> [[TMP8]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x i64> [[TMP5]], <4 x i64> [[TMP6]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
||||
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <4 x i64> [[TMP7]], <4 x i64> [[TMP8]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
||||
; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x i64> [[TMP9]], <4 x i64> [[TMP11]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i64> [[TMP10]], <4 x i64> [[TMP12]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
; CHECK-NEXT: [[TMP15:%.*]] = shufflevector <8 x i64> [[TMP13]], <8 x i64> [[TMP14]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
||||
; CHECK-NEXT: store <16 x i64> [[TMP15]], <16 x i64>* [[PTR:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
%s0 = shufflevector <4 x i64> %v0, <4 x i64> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
@ -136,8 +164,22 @@ define void @store_factorf64_4_revMask(<16 x double>* %ptr, <4 x double> %v0, <4
|
||||
; CHECK-LABEL: @store_factorf64_4_revMask(
|
||||
; CHECK-NEXT: [[S0:%.*]] = shufflevector <4 x double> [[V0:%.*]], <4 x double> [[V1:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
; CHECK-NEXT: [[S1:%.*]] = shufflevector <4 x double> [[V2:%.*]], <4 x double> [[V3:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <8 x double> [[S0]], <8 x double> [[S1]], <16 x i32> <i32 12, i32 8, i32 4, i32 0, i32 13, i32 9, i32 5, i32 1, i32 14, i32 10, i32 6, i32 2, i32 15, i32 11, i32 7, i32 3>
|
||||
; CHECK-NEXT: store <16 x double> [[INTERLEAVED_VEC]], <16 x double>* [[PTR:%.*]], align 16
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x double> [[S0]], <8 x double> [[S1]], <4 x i32> <i32 12, i32 13, i32 14, i32 15>
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x double> [[S0]], <8 x double> [[S1]], <4 x i32> <i32 8, i32 9, i32 10, i32 11>
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x double> [[S0]], <8 x double> [[S1]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x double> [[S0]], <8 x double> [[S1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x double> [[TMP1]], <4 x double> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x double> [[TMP1]], <4 x double> [[TMP3]], <4 x i32> <i32 2, i32 3, i32 6, i32 7>
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> [[TMP4]], <4 x i32> <i32 2, i32 3, i32 6, i32 7>
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x double> [[TMP5]], <4 x double> [[TMP6]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <4 x double> [[TMP7]], <4 x double> [[TMP8]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x double> [[TMP5]], <4 x double> [[TMP6]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
||||
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <4 x double> [[TMP7]], <4 x double> [[TMP8]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
||||
; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x double> [[TMP9]], <4 x double> [[TMP11]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x double> [[TMP10]], <4 x double> [[TMP12]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
; CHECK-NEXT: [[TMP15:%.*]] = shufflevector <8 x double> [[TMP13]], <8 x double> [[TMP14]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
||||
; CHECK-NEXT: store <16 x double> [[TMP15]], <16 x double>* [[PTR:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
%s0 = shufflevector <4 x double> %v0, <4 x double> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
@ -151,8 +193,22 @@ define void @store_factorf64_4_arbitraryMask(<16 x double>* %ptr, <16 x double>
|
||||
; CHECK-LABEL: @store_factorf64_4_arbitraryMask(
|
||||
; CHECK-NEXT: [[S0:%.*]] = shufflevector <16 x double> [[V0:%.*]], <16 x double> [[V1:%.*]], <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
|
||||
; CHECK-NEXT: [[S1:%.*]] = shufflevector <16 x double> [[V2:%.*]], <16 x double> [[V3:%.*]], <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
|
||||
; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <32 x double> [[S0]], <32 x double> [[S1]], <16 x i32> <i32 4, i32 32, i32 16, i32 8, i32 5, i32 33, i32 17, i32 9, i32 6, i32 34, i32 18, i32 10, i32 7, i32 35, i32 19, i32 11>
|
||||
; CHECK-NEXT: store <16 x double> [[INTERLEAVED_VEC]], <16 x double>* [[PTR:%.*]], align 16
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <32 x double> [[S0]], <32 x double> [[S1]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <32 x double> [[S0]], <32 x double> [[S1]], <4 x i32> <i32 32, i32 33, i32 34, i32 35>
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <32 x double> [[S0]], <32 x double> [[S1]], <4 x i32> <i32 16, i32 17, i32 18, i32 19>
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <32 x double> [[S0]], <32 x double> [[S1]], <4 x i32> <i32 8, i32 9, i32 10, i32 11>
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x double> [[TMP1]], <4 x double> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x double> [[TMP1]], <4 x double> [[TMP3]], <4 x i32> <i32 2, i32 3, i32 6, i32 7>
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> [[TMP4]], <4 x i32> <i32 2, i32 3, i32 6, i32 7>
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x double> [[TMP5]], <4 x double> [[TMP6]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <4 x double> [[TMP7]], <4 x double> [[TMP8]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x double> [[TMP5]], <4 x double> [[TMP6]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
||||
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <4 x double> [[TMP7]], <4 x double> [[TMP8]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
||||
; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x double> [[TMP9]], <4 x double> [[TMP11]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x double> [[TMP10]], <4 x double> [[TMP12]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
; CHECK-NEXT: [[TMP15:%.*]] = shufflevector <8 x double> [[TMP13]], <8 x double> [[TMP14]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
||||
; CHECK-NEXT: store <16 x double> [[TMP15]], <16 x double>* [[PTR:%.*]], align 16
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
%s0 = shufflevector <16 x double> %v0, <16 x double> %v1, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
|
||||
@ -161,4 +217,3 @@ define void @store_factorf64_4_arbitraryMask(<16 x double>* %ptr, <16 x double>
|
||||
store <16 x double> %interleaved.vec, <16 x double>* %ptr, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user