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[mips] [IAS] Refactor symbol-address loading code into a helper function. NFC.

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Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9523

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239811 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Toma Tabacu 2015-06-16 12:16:24 +00:00
parent a8cc053519
commit e8601cf932
1 changed files with 23 additions and 17 deletions
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40
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
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@ -186,6 +186,10 @@ class MipsAsmParser : public MCTargetAsmParser {
bool Is32BitImm, SMLoc IDLoc, bool Is32BitImm, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions); SmallVectorImpl<MCInst> &Instructions);
bool loadSymbolAddress(const MCExpr *SymExpr, unsigned DstReg,
bool Is32BitSym, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions);
bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions); SmallVectorImpl<MCInst> &Instructions);
@ -197,10 +201,6 @@ class MipsAsmParser : public MCTargetAsmParser {
bool expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, bool expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions); SmallVectorImpl<MCInst> &Instructions);
void expandLoadAddressSym(const MCOperand &DstRegOp, const MCOperand &SymOp,
bool Is32BitSym, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions);
void expandMemInst(MCInst &Inst, SMLoc IDLoc, void expandMemInst(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions, bool isLoad, SmallVectorImpl<MCInst> &Instructions, bool isLoad,
bool isImmOpnd); bool isImmOpnd);
@ -1913,7 +1913,10 @@ MipsAsmParser::expandLoadAddressReg(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
assert((ImmOp.isImm() || ImmOp.isExpr()) && assert((ImmOp.isImm() || ImmOp.isExpr()) &&
"expected immediate operand kind"); "expected immediate operand kind");
if (!ImmOp.isImm()) { if (!ImmOp.isImm()) {
expandLoadAddressSym(DstRegOp, ImmOp, Is32BitImm, IDLoc, Instructions); if (loadSymbolAddress(ImmOp.getExpr(), DstRegOp.getReg(), Is32BitImm, IDLoc,
Instructions))
return true;
return false; return false;
} }
const MCOperand &SrcRegOp = Inst.getOperand(1); const MCOperand &SrcRegOp = Inst.getOperand(1);
@ -1936,7 +1939,10 @@ MipsAsmParser::expandLoadAddressImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
assert((ImmOp.isImm() || ImmOp.isExpr()) && assert((ImmOp.isImm() || ImmOp.isExpr()) &&
"expected immediate operand kind"); "expected immediate operand kind");
if (!ImmOp.isImm()) { if (!ImmOp.isImm()) {
expandLoadAddressSym(DstRegOp, ImmOp, Is32BitImm, IDLoc, Instructions); if (loadSymbolAddress(ImmOp.getExpr(), DstRegOp.getReg(), Is32BitImm, IDLoc,
Instructions))
return true;
return false; return false;
} }
@ -1947,17 +1953,16 @@ MipsAsmParser::expandLoadAddressImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
return false; return false;
} }
void MipsAsmParser::expandLoadAddressSym( bool MipsAsmParser::loadSymbolAddress(const MCExpr *SymExpr, unsigned DstReg,
const MCOperand &DstRegOp, const MCOperand &SymOp, bool Is32BitSym, bool Is32BitSym, SMLoc IDLoc,
SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) { SmallVectorImpl<MCInst> &Instructions) {
warnIfNoMacro(IDLoc); warnIfNoMacro(IDLoc);
if (Is32BitSym && isABI_N64()) if (Is32BitSym && isABI_N64())
Warning(IDLoc, "instruction loads the 32-bit address of a 64-bit symbol"); Warning(IDLoc, "instruction loads the 32-bit address of a 64-bit symbol");
MCInst tmpInst; MCInst tmpInst;
unsigned RegNo = DstRegOp.getReg(); const MCSymbolRefExpr *Symbol = cast<MCSymbolRefExpr>(SymExpr);
const MCSymbolRefExpr *Symbol = cast<MCSymbolRefExpr>(SymOp.getExpr());
const MCSymbolRefExpr *HiExpr = const MCSymbolRefExpr *HiExpr =
MCSymbolRefExpr::create(Symbol->getSymbol().getName(), MCSymbolRefExpr::create(Symbol->getSymbol().getName(),
MCSymbolRefExpr::VK_Mips_ABS_HI, getContext()); MCSymbolRefExpr::VK_Mips_ABS_HI, getContext());
@ -1980,28 +1985,29 @@ void MipsAsmParser::expandLoadAddressSym(
MCSymbolRefExpr::VK_Mips_HIGHER, getContext()); MCSymbolRefExpr::VK_Mips_HIGHER, getContext());
tmpInst.setOpcode(Mips::LUi); tmpInst.setOpcode(Mips::LUi);
tmpInst.addOperand(MCOperand::createReg(RegNo)); tmpInst.addOperand(MCOperand::createReg(DstReg));
tmpInst.addOperand(MCOperand::createExpr(HighestExpr)); tmpInst.addOperand(MCOperand::createExpr(HighestExpr));
Instructions.push_back(tmpInst); Instructions.push_back(tmpInst);
createLShiftOri<0>(MCOperand::createExpr(HigherExpr), RegNo, SMLoc(), createLShiftOri<0>(MCOperand::createExpr(HigherExpr), DstReg, SMLoc(),
Instructions); Instructions);
createLShiftOri<16>(MCOperand::createExpr(HiExpr), RegNo, SMLoc(), createLShiftOri<16>(MCOperand::createExpr(HiExpr), DstReg, SMLoc(),
Instructions); Instructions);
createLShiftOri<16>(MCOperand::createExpr(LoExpr), RegNo, SMLoc(), createLShiftOri<16>(MCOperand::createExpr(LoExpr), DstReg, SMLoc(),
Instructions); Instructions);
} else { } else {
// Otherwise, expand to: // Otherwise, expand to:
// la d,sym => lui d,hi16(sym) // la d,sym => lui d,hi16(sym)
// ori d,d,lo16(sym) // ori d,d,lo16(sym)
tmpInst.setOpcode(Mips::LUi); tmpInst.setOpcode(Mips::LUi);
tmpInst.addOperand(MCOperand::createReg(RegNo)); tmpInst.addOperand(MCOperand::createReg(DstReg));
tmpInst.addOperand(MCOperand::createExpr(HiExpr)); tmpInst.addOperand(MCOperand::createExpr(HiExpr));
Instructions.push_back(tmpInst); Instructions.push_back(tmpInst);
createLShiftOri<0>(MCOperand::createExpr(LoExpr), RegNo, SMLoc(), createLShiftOri<0>(MCOperand::createExpr(LoExpr), DstReg, SMLoc(),
Instructions); Instructions);
} }
return false;
} }
bool MipsAsmParser::expandUncondBranchMMPseudo( bool MipsAsmParser::expandUncondBranchMMPseudo(