RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2025-02-15 18:49:51 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[AVX512] Add asm-only support for vextract*x4 masking variants

Browse Source 
These derive from the new asm-only masking definitions.

Unfortunately I wasn't able to find a ISel pattern that we could legally
generate for the masking variants.  The problem is that since the destination
is v4* we would need VK4 register classes and v4i1 value types to express the
masking.  These are however not legal types/classes in AVX512f but only in VL,
so things get complicated pretty quickly.  We can revisit this question later
if we have a more pressing need to express something like this.

So the ISel patterns are empty for the masking instructions and the next patch
will add Pat<>s instead to match the intrinsics calls with instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219361 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Adam Nemet 2014-10-08 23:25:33 +00:00
parent 9d0ec9212b
commit e868005a27
2 changed files with 27 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
lib/Target/X86/X86InstrAVX512.td
View File

@ -209,6 +209,18 @@ multiclass AVX512_masking_3src<bits<8> O, Format F, X86VectorVTInfo _,
OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
(vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
multiclass AVX512_masking_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
dag Outs, dag Ins,
string OpcodeStr,
string AttSrcAsm, string IntelSrcAsm,
list<dag> Pattern> :
AVX512_masking_custom<O, F, Outs, Ins,
!con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
!con((ins _.KRCWM:$mask), Ins),
OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
"$src0 = $dst">;
// Bitcasts between 512-bit vector types. Return the original type since
// no instruction is needed for the conversion
let Predicates = [HasAVX512] in {
@ -405,13 +417,13 @@ multiclass vextract_for_size<int Opcode,
PatFrag vextract_extract,
SDNodeXForm EXTRACT_get_vextract_imm> {
let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
def rr : AVX512AIi8<Opcode, MRMDestReg, (outs To.RC:$dst),
(ins VR512:$src1, i8imm:$idx),
"vextract" # To.EltTypeName # "x4\t{$idx, $src1, $dst|"
"$dst, $src1, $idx}",
[(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
(iPTR imm)))]>,
EVEX, EVEX_V512;
defm rr : AVX512_masking_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
(ins VR512:$src1, i8imm:$idx),
"vextract" # To.EltTypeName # "x4",
"$idx, $src1", "$src1, $idx",
[(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
(iPTR imm)))]>,
AVX512AIi8Base, EVEX, EVEX_V512;
let mayStore = 1 in
def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
(ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),

8
test/MC/X86/avx512-encodings.s
View File

@ -4335,3 +4335,11 @@ valignq $2, 0x100(%rsp), %zmm0, %zmm1
// CHECK: valignq $3
// CHECK: encoding: [0x62,0xf3,0xfd,0x49,0x03,0xcb,0x03]
valignq $3, %zmm3, %zmm0, %zmm1 {%k1}
// CHECK: vextractf32x4 $3
// CHECK: encoding: [0x62,0xf3,0x7d,0x49,0x19,0xd9,0x03]
vextractf32x4 $3, %zmm3, %xmm1 {%k1}
// CHECK: vextracti64x4 $1
// CHECK: encoding: [0x62,0x53,0xfd,0xcb,0x3b,0xf4,0x01]
vextracti64x4 $1, %zmm14, %ymm12 {%k3} {z}