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[SDAG] Don't widen VSETCC during type legalization for split operands

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Because the operands of a vector SETCC node can be of a different type from the
result (and often are), it can happen that even if we'd prefer to widen the
result type of the SETCC, the operands have been split instead. In this case,
the SETCC result also must be split. This mirrors what is done in
WidenVecRes_SELECT, and should be NFC elsewhere because if the operands are not
widened the following calls to GetWidenedVector will assert (which is what was
happening in the test case).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232935 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2015-03-23 08:22:43 +00:00
parent 858c62e51e
commit e86dbbf058
2 changed files with 50 additions and 0 deletions
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10
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -2553,6 +2553,16 @@ SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
assert(InVT.isVector() && "can not widen non-vector type");
EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
InVT.getVectorElementType(), WidenNumElts);
// The input and output types often differ here, and it could be that while
// we'd prefer to widen the result type, the input operands have been split.
// In this case, we also need to split the result of this node as well.
if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) {
SDValue SplitVSetCC = SplitVecOp_VSETCC(N);
SDValue Res = ModifyToType(SplitVSetCC, WidenVT);
return Res;
}
InOp1 = GetWidenedVector(InOp1);
SDValue InOp2 = GetWidenedVector(N->getOperand(1));

40
test/CodeGen/PowerPC/qpx-split-vsetcc.ll Normal file
View File

@ -0,0 +1,40 @@
; RUN: llc -mcpu=a2q < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-bgq-linux"
; Function Attrs: nounwind
define void @gsl_sf_legendre_Pl_deriv_array() #0 {
entry:
br i1 undef, label %do.body.i, label %if.else.i
do.body.i: ; preds = %entry
unreachable
if.else.i: ; preds = %entry
br i1 undef, label %return, label %for.body46.lr.ph
for.body46.lr.ph: ; preds = %if.else.i
br label %vector.body198
vector.body198: ; preds = %vector.body198, %for.body46.lr.ph
%0 = icmp ne <4 x i32> undef, zeroinitializer
%1 = select <4 x i1> %0, <4 x double> <double 5.000000e-01, double 5.000000e-01, double 5.000000e-01, double 5.000000e-01>, <4 x double> <double -5.000000e-01, double -5.000000e-01, double -5.000000e-01, double -5.000000e-01>
%2 = fmul <4 x double> undef, %1
%3 = fmul <4 x double> undef, %2
%4 = fmul <4 x double> %3, undef
store <4 x double> %4, <4 x double>* undef, align 8
br label %vector.body198
; CHECK-LABEL: @gsl_sf_legendre_Pl_deriv_array
; CHECK: qvlfiwzx
; CHECK: qvfcfidu
; CHECK: qvfcmpeq
; CHECK: qvfsel
; CHECK: qvfmul
return: ; preds = %if.else.i
ret void
}
attributes #0 = { nounwind }