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Don't repeat class/function/variable names in comments. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222555 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -40,7 +40,7 @@ using namespace llvm;
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#define DEBUG_TYPE "legalizedag"
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//===----------------------------------------------------------------------===//
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/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
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/// This takes an arbitrary SelectionDAG as input and
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/// hacks on it until the target machine can handle it. This involves
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/// eliminating value sizes the machine cannot handle (promoting small sizes to
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/// large sizes or splitting up large values into small values) as well as
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@ -86,7 +86,7 @@ private:
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void LegalizeLoadOps(SDNode *Node);
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void LegalizeStoreOps(SDNode *Node);
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/// PerformInsertVectorEltInMemory - Some target cannot handle a variable
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/// Some targets cannot handle a variable
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/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
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/// is necessary to spill the vector being inserted into to memory, perform
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/// the insert there, and then read the result back.
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@ -95,7 +95,7 @@ private:
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SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
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SDValue Idx, SDLoc dl);
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/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
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/// Return a vector shuffle operation which
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/// performs the same shuffe in terms of order or result bytes, but on a type
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/// whose vector element type is narrower than the original shuffle type.
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/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
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@ -200,7 +200,7 @@ public:
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};
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}
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/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
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/// Return a vector shuffle operation which
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/// performs the same shuffe in terms of order or result bytes, but on a type
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/// whose vector element type is narrower than the original shuffle type.
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/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
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@ -232,7 +232,7 @@ SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
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return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
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}
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/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
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/// Expands the ConstantFP node to an integer constant or
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/// a load from the constant pool.
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SDValue
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SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
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@ -286,7 +286,7 @@ SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
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return Result;
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}
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/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
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/// Expands an unaligned store to 2 half-size stores.
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static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
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const TargetLowering &TLI,
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SelectionDAGLegalize *DAGLegalize) {
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@ -409,7 +409,7 @@ static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
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DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
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}
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/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
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/// Expands an unaligned load to 2 half-size loads.
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static void
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ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
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const TargetLowering &TLI,
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@ -561,8 +561,8 @@ ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
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ChainResult = TF;
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}
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/// PerformInsertVectorEltInMemory - Some target cannot handle a variable
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/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
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/// Some target cannot handle a variable insertion index for the
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/// INSERT_VECTOR_ELT instruction. In this case, it
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/// is necessary to spill the vector being inserted into to memory, perform
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/// the insert there, and then read the result back.
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SDValue SelectionDAGLegalize::
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@ -1078,10 +1078,8 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
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unsigned AS = LD->getAddressSpace();
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unsigned Align = LD->getAlignment();
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if (!TLI.allowsMisalignedMemoryAccesses(MemVT, AS, Align)) {
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Type *Ty =
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LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
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unsigned ABIAlignment =
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TLI.getDataLayout()->getABITypeAlignment(Ty);
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Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
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unsigned ABIAlignment = TLI.getDataLayout()->getABITypeAlignment(Ty);
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if (Align < ABIAlignment){
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ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, Value, Chain);
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}
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@ -1090,10 +1088,8 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
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break;
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}
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case TargetLowering::Expand:
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if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) &&
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TLI.isTypeLegal(SrcVT)) {
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SDValue Load = DAG.getLoad(SrcVT, dl, Chain, Ptr,
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LD->getMemOperand());
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if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) {
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SDValue Load = DAG.getLoad(SrcVT, dl, Chain, Ptr, LD->getMemOperand());
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unsigned ExtendOp;
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switch (ExtType) {
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case ISD::EXTLOAD:
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@ -1151,8 +1147,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
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}
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}
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/// LegalizeOp - Return a legal replacement for the given operation, with
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/// all legal operands.
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/// Return a legal replacement for the given operation, with all legal operands.
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void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
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DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG));
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@ -1638,8 +1633,8 @@ void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
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Results.push_back(Tmp2);
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}
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/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
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/// condition code CC on the current target.
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/// Legalize a SETCC with given LHS and RHS and condition code CC on the current
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/// target.
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///
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/// If the SETCC has been legalized using AND / OR, then the legalized node
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/// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
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@ -1753,7 +1748,7 @@ bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
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return false;
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}
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/// EmitStackConvert - Emit a store/load combination to the stack. This stores
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/// Emit a store/load combination to the stack. This stores
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/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
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/// a load from the stack slot to DestVT, extending it if needed.
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/// The resultant code need not be legal.
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@ -1913,7 +1908,7 @@ ExpandBVWithShuffles(SDNode *Node, SelectionDAG &DAG,
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return true;
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}
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/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
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/// Expand a BUILD_VECTOR node on targets that don't
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/// support the operation, but do support the resultant vector type.
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SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
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unsigned NumElems = Node->getNumOperands();
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@ -2025,7 +2020,7 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
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return ExpandVectorBuildThroughStack(Node);
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}
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// ExpandLibCall - Expand a node into a call to a libcall. If the result value
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// Expand a node into a call to a libcall. If the result value
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// does not fit into a register, return the lo part and set the hi part to the
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// by-reg argument. If it does fit into a single register, return the result
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// and leave the Hi part unset.
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@ -2073,7 +2068,7 @@ SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
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return CallInfo.first;
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}
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/// ExpandLibCall - Generate a libcall taking the given operands as arguments
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/// Generate a libcall taking the given operands as arguments
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/// and returning a result of type RetVT.
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SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
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const SDValue *Ops, unsigned NumOps,
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@ -2104,7 +2099,7 @@ SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
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return CallInfo.first;
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}
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// ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
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// Expand a node into a call to a libcall. Similar to
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// ExpandLibCall except that the first operand is the in-chain.
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std::pair<SDValue, SDValue>
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SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
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@ -2174,7 +2169,7 @@ SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
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return ExpandLibCall(LC, Node, isSigned);
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}
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/// isDivRemLibcallAvailable - Return true if divmod libcall is available.
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/// Return true if divmod libcall is available.
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static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
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const TargetLowering &TLI) {
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RTLIB::Libcall LC;
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@ -2190,8 +2185,7 @@ static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
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return TLI.getLibcallName(LC) != nullptr;
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}
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/// useDivRem - Only issue divrem libcall if both quotient and remainder are
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/// needed.
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/// Only issue divrem libcall if both quotient and remainder are needed.
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static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
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// The other use might have been replaced with a divrem already.
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unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
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@ -2216,8 +2210,7 @@ static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
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return false;
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}
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/// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
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/// pairs.
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/// Issue libcalls to __{u}divmod to compute div / rem pairs.
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void
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SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
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SmallVectorImpl<SDValue> &Results) {
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@ -2279,7 +2272,7 @@ SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
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Results.push_back(Rem);
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}
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/// isSinCosLibcallAvailable - Return true if sincos libcall is available.
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/// Return true if sincos libcall is available.
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static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
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RTLIB::Libcall LC;
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switch (Node->getSimpleValueType(0).SimpleTy) {
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@ -2293,8 +2286,8 @@ static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
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return TLI.getLibcallName(LC) != nullptr;
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}
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/// canCombineSinCosLibcall - Return true if sincos libcall is available and
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/// can be used to combine sin and cos.
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/// Return true if sincos libcall is available and can be used to combine sin
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/// and cos.
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static bool canCombineSinCosLibcall(SDNode *Node, const TargetLowering &TLI,
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const TargetMachine &TM) {
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if (!isSinCosLibcallAvailable(Node, TLI))
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@ -2307,8 +2300,7 @@ static bool canCombineSinCosLibcall(SDNode *Node, const TargetLowering &TLI,
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return true;
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}
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/// useSinCos - Only issue sincos libcall if both sin and cos are
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/// needed.
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/// Only issue sincos libcall if both sin and cos are needed.
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static bool useSinCos(SDNode *Node) {
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unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
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? ISD::FCOS : ISD::FSIN;
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@ -2326,8 +2318,7 @@ static bool useSinCos(SDNode *Node) {
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return false;
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}
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/// ExpandSinCosLibCall - Issue libcalls to sincos to compute sin / cos
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/// pairs.
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/// Issue libcalls to sincos to compute sin / cos pairs.
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void
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SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
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SmallVectorImpl<SDValue> &Results) {
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@ -2392,7 +2383,7 @@ SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
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MachinePointerInfo(), false, false, false, 0));
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}
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/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
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/// This function is responsible for legalizing a
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/// INT_TO_FP operation of the specified operand when the target requests that
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/// we expand it. At this point, we know that the result and operand types are
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/// legal for the target.
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@ -2590,7 +2581,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
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return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
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}
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/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
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/// This function is responsible for legalizing a
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/// *INT_TO_FP operation of the specified operand when the target requests that
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/// we promote it. At this point, we know that the result and operand types are
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/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
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@ -2632,7 +2623,7 @@ SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
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dl, NewInTy, LegalOp));
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}
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/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
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/// This function is responsible for legalizing a
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/// FP_TO_*INT operation of the specified operand when the target requests that
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/// we promote it. At this point, we know that the result and operand types are
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/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
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@ -2676,8 +2667,7 @@ SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
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return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
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}
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/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
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///
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/// Open code the operations for BSWAP of the specified operation.
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SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) {
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EVT VT = Op.getValueType();
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EVT SHVT = TLI.getShiftAmountTy(VT);
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@ -2723,8 +2713,7 @@ SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) {
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}
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}
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/// ExpandBitCount - Expand the specified bitcount instruction into operations.
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///
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/// Expand the specified bitcount instruction into operations.
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SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
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SDLoc dl) {
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switch (Opc) {
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@ -4315,8 +4304,7 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
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ReplaceNode(Node, Results.data());
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}
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// SelectionDAG::Legalize - This is the entry point for the file.
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//
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/// This is the entry point for the file.
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void SelectionDAG::Legalize() {
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AssignTopologicalOrder();
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