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Reverted revisions 221351, 221352 and 221353.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221354 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zoran Jovanovic 2014-11-05 16:19:59 +00:00
parent e7ec22de06
commit e9b9ca452f
10 changed files with 11 additions and 173 deletions
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10
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
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@ -1198,16 +1198,6 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
if (Imm < 0 || Imm > 255)
return Error(IDLoc, "immediate operand value out of range");
break;
case Mips::ANDI16_MM:
Opnd = Inst.getOperand(2);
if (!Opnd.isImm())
return Error(IDLoc, "expected immediate operand kind");
Imm = Opnd.getImm();
if (!(Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535))
return Error(IDLoc, "immediate operand value out of range");
break;
}
}

28
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
View File

@ -729,32 +729,4 @@ MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
return MO.getImm() % 8;
}
unsigned
MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
assert(MI.getOperand(OpNo).isImm());
const MCOperand &MO = MI.getOperand(OpNo);
unsigned Value = MO.getImm();
switch (Value) {
case 128: return 0x0;
case 1: return 0x1;
case 2: return 0x2;
case 3: return 0x3;
case 4: return 0x4;
case 7: return 0x5;
case 8: return 0x6;
case 15: return 0x7;
case 16: return 0x8;
case 31: return 0x9;
case 32: return 0xa;
case 63: return 0xb;
case 64: return 0xc;
case 255: return 0xd;
case 32768: return 0xe;
case 65535: return 0xf;
default: assert(0 && "Unexpected value");
}
}
#include "MipsGenMCCodeEmitter.inc"

3
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
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@ -168,9 +168,6 @@ public:
unsigned getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getUImm4AndValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;

13
lib/Target/Mips/MicroMipsInstrFormats.td
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@ -55,19 +55,6 @@ class ARITH_FM_MM16<bit funct> {
let Inst{0} = funct;
}
class ANDI_FM_MM16<bits<6> funct> {
bits<3> rd;
bits<3> rs;
bits<4> imm;
bits<16> Inst;
let Inst{15-10} = funct;
let Inst{9-7} = rd;
let Inst{6-4} = rs;
let Inst{3-0} = imm;
}
class LOGIC_FM_MM16<bits<4> funct> {
bits<3> rt;
bits<3> rs;

49
lib/Target/Mips/MicroMipsInstrInfo.td
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@ -27,15 +27,6 @@ def simm3_lsa2 : Operand<i32> {
let EncoderMethod = "getSImm3Lsa2Value";
}
def uimm4_andi : Operand<i32> {
let EncoderMethod = "getUImm4AndValue";
}
def immZExtAndi16 : ImmLeaf<i32,
[{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );}]>;
def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>;
def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>;
@ -125,11 +116,6 @@ class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
let isCommutable = isComm;
}
class AndImmMM16<string opstr, RegisterOperand RO,
InstrItinClass Itin = NoItinerary> :
MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
!strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;
class LogicRMM16<string opstr, RegisterOperand RO,
InstrItinClass Itin = NoItinerary,
SDPatternOperator OpNode = null_frag> :
@ -145,10 +131,13 @@ class NotMM16<string opstr, RegisterOperand RO> :
!strconcat(opstr, "\t$rt, $rs"),
[(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>;
class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
class ShiftIMM16<string opstr, Operand ImmOpnd,
RegisterOperand RO, SDPatternOperator OpNode = null_frag,
SDPatternOperator PF = null_frag,
InstrItinClass Itin = NoItinerary> :
MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
!strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
!strconcat(opstr, "\t$rd, $rt, $shamt"),
[(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], Itin, FrmR>;
class AddImmUR2<string opstr, RegisterOperand RO> :
MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
@ -264,7 +253,6 @@ def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
ARITH_FM_MM16<0>;
def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
ARITH_FM_MM16<1>;
def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>;
def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
LOGIC_FM_MM16<0x2>;
def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
@ -272,10 +260,10 @@ def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
LOGIC_FM_MM16<0x1>;
def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>;
def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
SHIFT_FM_MM16<0>;
def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
SHIFT_FM_MM16<1>;
def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, shl,
immZExt2Shift, II_SLL>, SHIFT_FM_MM16<0>;
def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, srl,
immZExt2Shift, II_SRL>, SHIFT_FM_MM16<1>;
def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16;
def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
@ -510,25 +498,6 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
}
//===----------------------------------------------------------------------===//
// MicroMips arbitrary patterns that map to one or more instructions
//===----------------------------------------------------------------------===//
def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
(ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>;
def : MipsPat<(and GPR32:$src, immZExt16:$imm),
(ANDi_MM GPR32:$src, immZExt16:$imm)>;
def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm),
(SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
(SLL_MM GPR32:$src, immZExt5:$imm)>;
def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
(SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
(SRL_MM GPR32:$src, immZExt5:$imm)>;
//===----------------------------------------------------------------------===//
// MicroMips instruction aliases
//===----------------------------------------------------------------------===//

7
lib/Target/Mips/MipsInstrInfo.td
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@ -1105,10 +1105,9 @@ def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
SLTI_FM<0xa>;
def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
SLTI_FM<0xb>;
let AdditionalPredicates = [NotInMicroMips] in {
def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
and>, ADDI_FM<0xc>;
}
and>,
ADDI_FM<0xc>;
def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
or>,
ADDI_FM<0xd>;
@ -1138,12 +1137,10 @@ def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
/// Shift Instructions
let AdditionalPredicates = [NotInMicroMips] in {
def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
immZExt5>, SRA_FM<0, 0>;
def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
immZExt5>, SRA_FM<2, 0>;
}
def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
immZExt5>, SRA_FM<3, 0>;
def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,

25
test/CodeGen/Mips/micromips-andi.ll
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@ -1,25 +0,0 @@
; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
@x = global i32 65504, align 4
@y = global i32 60929, align 4
@.str = private unnamed_addr constant [7 x i8] c"%08x \0A\00", align 1
define i32 @main() nounwind {
entry:
%0 = load i32* @x, align 4
%and1 = and i32 %0, 4
%call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds
([7 x i8]* @.str, i32 0, i32 0), i32 %and1)
%1 = load i32* @y, align 4
%and2 = and i32 %1, 5
%call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds
([7 x i8]* @.str, i32 0, i32 0), i32 %and2)
ret i32 0
}
declare i32 @printf(i8*, ...)
; CHECK: andi16 ${{[2-7]|16|17}}, ${{[2-7]|16|17}}
; CHECK: andi ${{[0-9]+}}, ${{[0-9]+}}

44
test/CodeGen/Mips/micromips-shift.ll
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@ -1,44 +0,0 @@
; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
@a = global i32 10, align 4
@b = global i32 0, align 4
@c = global i32 10, align 4
@d = global i32 0, align 4
define i32 @shift_left() nounwind {
entry:
%0 = load i32* @a, align 4
%shl = shl i32 %0, 4
store i32 %shl, i32* @b, align 4
%1 = load i32* @c, align 4
%shl1 = shl i32 %1, 10
store i32 %shl1, i32* @d, align 4
ret i32 0
}
; CHECK: sll16 ${{[2-7]|16|17}}, ${{[2-7]|16|17}}, {{[0-7]}}
; CHECK: sll ${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}}
@i = global i32 10654, align 4
@j = global i32 0, align 4
@m = global i32 10, align 4
@n = global i32 0, align 4
define i32 @shift_right() nounwind {
entry:
%0 = load i32* @i, align 4
%shr = lshr i32 %0, 4
store i32 %shr, i32* @j, align 4
%1 = load i32* @m, align 4
%shr1 = lshr i32 %1, 10
store i32 %shr1, i32* @n, align 4
ret i32 0
}
; CHECK: srl16 ${{[2-7]|16|17}}, ${{[2-7]|16|17}}, {{[0-7]}}
; CHECK: srl ${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}}

3
test/MC/Mips/micromips-16-bit-instructions.s
View File

@ -11,7 +11,6 @@
#------------------------------------------------------------------------------
# CHECK-EL: addu16 $6, $17, $4 # encoding: [0x42,0x07]
# CHECK-EL: subu16 $5, $16, $3 # encoding: [0xb1,0x06]
# CHECK-EL: andi16 $16, $2, 31 # encoding: [0x29,0x2c]
# CHECK-EL: and16 $16, $2 # encoding: [0x82,0x44]
# CHECK-EL: not16 $17, $3 # encoding: [0x0b,0x44]
# CHECK-EL: or16 $16, $4 # encoding: [0xc4,0x44]
@ -41,7 +40,6 @@
#------------------------------------------------------------------------------
# CHECK-EB: addu16 $6, $17, $4 # encoding: [0x07,0x42]
# CHECK-EB: subu16 $5, $16, $3 # encoding: [0x06,0xb1]
# CHECK-EB: andi16 $16, $2, 31 # encoding: [0x2c,0x29]
# CHECK-EB: and16 $16, $2 # encoding: [0x44,0x82]
# CHECK-EB: not16 $17, $3 # encoding: [0x44,0x0b]
# CHECK-EB: or16 $16, $4 # encoding: [0x44,0xc4]
@ -69,7 +67,6 @@
addu16 $6, $17, $4
subu16 $5, $16, $3
andi16 $16, $2, 31
and16 $16, $2
not16 $17, $3
or16 $16, $4

2
test/MC/Mips/micromips-invalid.s
View File

@ -8,8 +8,6 @@
addiusp 1032 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
addu16 $6, $14, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
subu16 $5, $16, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
andi16 $16, $10, 0x1f # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
andi16 $16, $2, 17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
and16 $16, $8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
not16 $18, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
or16 $16, $10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction