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[PowerPC] - No SExt/ZExt needed for count trailing zeros

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This patch corresponds to review:
https://reviews.llvm.org/D25896

It just eliminates the redundant ZExt after a count trailing zeros instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285267 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nemanja Ivanovic 2016-10-27 05:17:58 +00:00
parent 56a90b623f
commit e9fdaa1bbb
2 changed files with 58 additions and 2 deletions
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6
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -4041,8 +4041,9 @@ static bool PeepholePPC64ZExtGather(SDValue Op32,
return true;
}
// CNTLZW always produces a 64-bit value in [0,32], and so is zero extended.
if (Op32.getMachineOpcode() == PPC::CNTLZW) {
// CNT[LT]ZW always produce a 64-bit value in [0,32], and so is zero extended.
if (Op32.getMachineOpcode() == PPC::CNTLZW ||
Op32.getMachineOpcode() == PPC::CNTTZW) {
ToPromote.insert(Op32.getNode());
return true;
}
@ -4237,6 +4238,7 @@ void PPCDAGToDAGISel::PeepholePPC64ZExt() {
case PPC::LHBRX: NewOpcode = PPC::LHBRX8; break;
case PPC::LWBRX: NewOpcode = PPC::LWBRX8; break;
case PPC::CNTLZW: NewOpcode = PPC::CNTLZW8; break;
case PPC::CNTTZW: NewOpcode = PPC::CNTTZW8; break;
case PPC::RLWIMI: NewOpcode = PPC::RLWIMI8; break;
case PPC::OR: NewOpcode = PPC::OR8; break;
case PPC::SELECT_I4: NewOpcode = PPC::SELECT_I8; break;

54
test/CodeGen/PowerPC/no-ext-with-count-zeros.ll Normal file
View File

@ -0,0 +1,54 @@
; Function Attrs: nounwind readnone
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
; RUN: -mcpu=pwr9 < %s | FileCheck %s
define signext i32 @ctw(i32 signext %a) {
entry:
%0 = tail call i32 @llvm.cttz.i32(i32 %a, i1 false)
ret i32 %0
; CHECK-LABEL: ctw
; CHECK: cnttzw 3, 3
; CHECK-NEXT: blr
}
; Function Attrs: nounwind readnone
declare i32 @llvm.cttz.i32(i32, i1)
; Function Attrs: nounwind readnone
define signext i32 @clw(i32 signext %a) {
entry:
%0 = tail call i32 @llvm.ctlz.i32(i32 %a, i1 false)
ret i32 %0
; CHECK-LABEL: clw
; CHECK: cntlzw 3, 3
; CHECK-NEXT: blr
}
; Function Attrs: nounwind readnone
declare i32 @llvm.ctlz.i32(i32, i1)
; Function Attrs: nounwind readnone
define i64 @ctd(i64 %a) {
entry:
%0 = tail call i64 @llvm.cttz.i64(i64 %a, i1 false)
ret i64 %0
; CHECK-LABEL: ctd
; CHECK: cnttzd 3, 3
; CHECK-NEXT: blr
}
; Function Attrs: nounwind readnone
declare i64 @llvm.cttz.i64(i64, i1)
; Function Attrs: nounwind readnone
define i64 @cld(i64 %a) {
entry:
%0 = tail call i64 @llvm.ctlz.i64(i64 %a, i1 false)
ret i64 %0
; CHECK-LABEL: cld
; CHECK: cntlzd 3, 3
; CHECK-NEXT: blr
}
; Function Attrs: nounwind readnone
declare i64 @llvm.ctlz.i64(i64, i1)