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AMDGPU/GCN: Exit early in hazard recognizer if there is no vreg argument

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wbinvl.* are vector instruction that do not sue vector registers.

v2: check only M?BUF instructions

Differential Revision: https://reviews.llvm.org/D26633

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287056 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jan Vesely 2016-11-15 23:55:15 +00:00
parent e9b0d8061c
commit ea73d16588
2 changed files with 7 additions and 1 deletions
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4
lib/Target/AMDGPU/GCNHazardRecognizer.cpp
View File

@ -400,6 +400,10 @@ int GCNHazardRecognizer::createsVALUHazard(const MachineInstr &MI) {
VDataRCID = Desc.OpInfo[VDataIdx].RegClass;
if (TII->isMUBUF(MI) || TII->isMTBUF(MI)) {
// There is no hazard if the instruction does not use vector regs
// (like wbinvl1)
if (VDataIdx == -1)
return -1;
// For MUBUF/MTBUF instructions this hazard only exists if the
// instruction is not using a register in the soffset field.
const MachineOperand *SOffset =

4
test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.vol.ll
View File

@ -7,9 +7,11 @@ declare void @llvm.amdgcn.buffer.wbinvl1.vol() #0
; GCN-NEXT: ; BB#0:
; CI-NEXT: buffer_wbinvl1_vol ; encoding: [0x00,0x00,0xc0,0xe1,0x00,0x00,0x00,0x00]
; VI-NEXT: buffer_wbinvl1_vol ; encoding: [0x00,0x00,0xfc,0xe0,0x00,0x00,0x00,0x00]
; GCN-NEXT: s_endpgm
; GCN: s_endpgm
define void @test_buffer_wbinvl1_vol() #0 {
call void @llvm.amdgcn.buffer.wbinvl1.vol()
; This used to crash in hazard recognizer
store i8 0, i8 addrspace(1)* undef, align 1
ret void
}